Intel Corporation

Camron B Rust

Gilbert A Neiger

Andrew V Anderson

Richard A Uhlig

Steven M Bennett

Rajesh M Sankaran

Sebastian Schoenberg

Scott Dion Rodgers

Dion Rodgers

Rupin H Vakharwala

David A Koufaty

Martin Guy Dixon

Frank Binns

Thomas P Thomas

Manpreet Singh Khaira

Hermann Gartler

Larry O Smith

Eric Gouldey

David Finan

Brett Ireland

Rajesh Madukkaraumukumana

Embodiments of the present disclosure may be related to an electronic device that includes a root complex; and a processor coupled with the root complex. The root complex may identify a first direct memory access (DMA) transaction and a second DMA transaction respectively related to a first task and a second task of a device communicatively coupled with the root complex through an input/output (I/O) fabric. The root complex may further cache a first memory translation related to the first DMA transaction in a first micro translation lookaside buffer (uTLB) of the root complex. The root complex may further cache a second memory translation related to the second DMA transaction in a second uTLB of the root complex. Other embodiments may be described and/or claimed.

Input/output translation lookaside buffer (IOTLB) quality of service (QoS)

A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

Synchronizing a translation lookaside buffer with an extended paging table

Embodiments of apparatuses, methods, and systems for input/output translation lookaside buffer (IOTLB) prefetching are described. In an embodiment, an apparatus includes a bridge, an input/output memory management unit (IOMMU), and an IOTLB prefetch unit. The bridge is between an input/output (I/O) side of a system and a memory side of the system. The I/O side is to include an interconnect on which a zero-length transaction is to be initiated by an I/O device. The zero-length transaction is to include an I/O-side memory address. The IOMMU includes address translation hardware and an IOTLB. The address translation hardware is to generate a translation of the I/O-side memory address to a memory-side memory address. The translation is to be stored in the IOTLB. The IOTLB prefetch control unit includes prefetch control logic to cause the apparatus to, in response to determining that the memory-side address is inaccessible, emulate completion of the zero-length transaction.

Input/output translation lookaside buffer prefetching

Growing community of inventors

Hillsboro, OR, United States of America

Camron B Rust