Altera Corporation

Other

Cameron R McClintock

Richard G Cliff

Andy Louie Lee

Srinivas T Reddy

William W Leong

Christopher F Lane

Brian D Johnson

Bruce B Pedersen

Bahram Ahanin

James A Watson

David Lewis

Joseph Huang

Paul Leventis

Vaughn Betz

L Todd Cope

Bonnie I Wang

Wanli Chang

David Edward Jefferson

Francis B Heile

Ketan H Zaveri

Chiakang Sung

Ninh D Ngo

Manuel M Mejia

Fung Fung Lee

Richard Yen-Hsiang Chang

David Wolk Mendel

Kerry S Veenstra

John E Turner

Chiao Kai Hwang

Chris Lane

James G Schleicher

David Chiang

Hock-Chuen So

Chris Wysocki

Giles V Powell

Michael Chan

Alexander Marquardt

Kurosu R Altaf

Hock C So

Richard Y Chang

Triet M Nguyen

Stephanie T Tran

Toan Thanh Nguyen

Bruce B Pederson

Ken Ming Li

Caleb Crome

Hiten S Randhawa

Risa Altaf

In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.

PLD architecture for flexible placement of IP function blocks

A programmable logic device (PLD) includes at least two regions. Each region includes electrical circuitry that has a set of transistors. Each of the two regions has a corresponding fixed transistor threshold voltage, a corresponding fixed transistor body bias, and a corresponding fixed supply voltage.

Apparatus and methods for adjusting performance of programmable logic devices

Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Von the range of signals passed by single-transistor passgates is reduced. In one arrangement, the V-Vlimit for signals propagated through NMOS passgates is raised by applying a higher V; in another arrangement, the Vis lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.

Passgate structures for use in low-voltage applications

Techniques are provided for increasing flexibility to I/O banks with respect to supply voltages. Multiple supply voltages can be provided to a bank of I/O pins. Separate I/O pins residing in an I/O bank are driven by buffers that are coupled to different supply voltages. Dedicated I/O pins are driven by buffers with pre-selected supply voltages. The dedicated I/O pins can be grouped together into the same I/O bank providing greater flexibility to drive signals on I/O pins in other I/O banks at different voltages. Also, a dual mode input buffer can drive an input signal to a voltage determined by one of two possible supply voltage levels. In addition, power on reset circuits for an I/O bank can monitor the voltage of two or more supply voltages.

Techniques for providing increased flexibility to input/output banks with respect to supply voltages

Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Von the range of signals passed by single-transistor passgates is reduced. In one arrangement, the V&#x2212;Vlimit for signals propagated through NMOS passgates is raised by applying a higher V; in another arrangement, the Vis lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.

Passage structures for use in low-voltage applications

Methods for designing PLD architectures for flexible placement of IP function blocks

Circuitry is provided to individually configure each I/O of an integrated circuit to be compatible with a different LVTTL I/O standards. This can be done with only one I/O supply voltage, where that voltage is the highest of the I/O voltages needed in a particular application. The circuitry operates by regulating the output voltage of the I/O cell so that it is above the VOH and below the maximum VIH for the LVTTL standard for which it will comply with. Since each I/O cell is individually configurable, any I/O can drive out to any LVTTL specification.

I/O cell configuration for multiple I/O standards

An embodiment of this invention pertains to a 3-sided routing architecture to interconnect function blocks, such as logic array blocks ('LABs'), within a programmable logic device ('PLD'). In the 3-sided routing architecture, inputs and outputs on a first side of a function block connect to a first channel, and inputs and outputs on a second side of the function block connect to a second channel where the second side is opposite the first side. Inputs and outputs on a third side of the function block connect to a third channel. A fourth channel associated with a fourth side of the function block, the fourth side opposite the third side, is coupled only to the first channel and the second channel. In one configuration, the inputs and outputs on each of the first side, the second side, and the third side have an equal number of inputs and outputs. In this configuration, each of the first channel, the second channel, and the third channel have the same width. In another configuration, the number of pins on one of the first side, the second side, or the third side differs from the number of pins on another one of those sides.

Routing architecture for a programmable logic device

A programmable logic device is provided that contains circuitry that may be used for observing logic signals from programmable logic circuits on the device for testing the operation of the device. Circuitry is also provided that may be used for preloading data into various circuits on the device. The logic signal observing circuitry may allow registered signals to be observed, may allow combinatorial signals to be observed, or may allow both registered and combinatorial signals to be observed.

Programmable logic device with circuitry for observing programmable logic circuit signals and for preloading programmable logic circuits

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Mountain View, CA, United States of America

Cameron R McClintock