International Business Machines Corporation

Globalfoundries U.S. Inc.

Globalfoundries Inc.

Cameron E Luce

Anthony K Stamper

Christopher Vincent Jahnes

Eric Jeffrey White

William Joseph Murphy

Jeffrey C Maling

Michael T Brigham

Siva P Adusumilli

Ramsey M Hazbun

Steven M Shank

Pernell Dongmo

Jeffrey P Gambino

Vibhor Jain

Alvin Jose Joseph

Bucknell Chapman Webb

Mark Levy

Daniel Scott Vanslette

Qizhi Liu

Uppili S Raghunathan

Megan Elizabeth Lydon-Nuhfer

John J Ellis-Monaghan

Judson Robert Holt

James William Adkisson

John Joseph Pekarik

Rajendran Krishnasamy

Alexander M Derrickson

Sarah A McTaggart

Laura J Schutz

Jessica Anne Levy

Laura J Silverstein

Jacob M Deangelis

Sarah A Mctaggart

The disclosure provides an isolation stack for a bipolar transistor (BT), and related methods. A structure of the disclosure includes a first isolation layer on a subcollector. A first air gap is between the first isolation layer and a collector of a BT. A second isolation layer is on the first isolation layer and adjacent an intrinsic base of the BT. A third isolation layer is on the second isolation layer, vertically between the second isolation layer and an extrinsic base of the BT. A second air gap is adjacent the third isolation layer and below the extrinsic base.

Isolation stack for a bipolar transistor and related methods

The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor and methods of manufacture. The structure includes: a collector region; an extrinsic base comprising an emitter opening with an angled sidewall; an emitter within the emitter opening; and an intrinsic base between the emitter and the collector.

Bipolar transistor

Disclosed are semiconductor structure embodiments of a semiconductor-on-insulator region on a bulk substrate. The semiconductor-on-insulator region includes an upper semiconductor layer above and physically separated from the substrate by insulator-containing cavities (e.g., by dielectric layer and/or a pocket of trapped air, of trapped gas, or under vacuum) and, optionally, by a lower semiconductor layer. Disclosed method embodiments include forming openings that extend vertically through the upper semiconductor layer, through a sacrificial semiconductor layer and, optionally, through a lower semiconductor layer to the substrate. Then, a selective isotropic etch process is performed to form cavities, which extend laterally off the sides of the openings into the sacrificial semiconductor layer. Depending upon the embodiments, different process steps are further performed to form plugs in at least the upper portions of the openings and insulators (including dielectric layers and/or a pocket of trapped air, of trapped gas or under vacuum) in the cavities.

Semiconductor structure with semiconductor-on-insulator region and method

Structures for a microfluidic channel and methods of forming a structure for a microfluidic channel. The structure comprises a trench in a semiconductor substrate and a semiconductor layer inside the trench. The trench has an entrance and a sidewall extending from the entrance into the semiconductor substrate. The semiconductor layer has a first portion surrounding a portion of the trench to define a cavity and a second portion positioned to obstruct the entrance to the trench. The second portion of the semiconductor layer is thicker than the first portion of the semiconductor layer.

Microfluidic channels sealed with directionally-grown plugs

The present disclosure relates to semiconductor structures and, more particularly, to an avalanche photodiode and methods of manufacture. The structure includes: a substrate material having a trench with sidewalls and a bottom composed of the substrate material; a first semiconductor material lining the sidewalls and the bottom of the trench; a photosensitive semiconductor material provided on the first semiconductor material; and a third semiconductor material provided on the photosensitive semiconductor material.

Avalanche photodiode

Methods of forming structures with electrical isolation. A dielectric layer is formed over a semiconductor substrate, openings are patterned in the dielectric layer that extend to the semiconductor substrate, and a semiconductor material is epitaxially grown from portions of the semiconductor substrate that are respectively exposed inside the openings. The semiconductor material, during growth, defines a semiconductor layer that includes first portions respectively coincident with the openings and second portions that laterally grow from the first portions to merge over a top surface of the dielectric layer. A modified layer containing a trap-rich semiconductor material is formed in the semiconductor substrate.

Epitaxial growth constrained by a template

The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes: a sub-collector region in a substrate; a collector region above the sub-collector region, the collector region composed of semiconductor material; an intrinsic base region composed of intrinsic base material surrounded by the semiconductor material above the collector region; and an emitter region above the intrinsic base region.

Heterojunction bipolar transistors

Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both tungsten material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam.

Micro-electro-mechanical system (MEMS) structures and design structures

The present disclosure relates to semiconductor structures and, more particularly, to sealed cavity structures having a planar surface and methods of manufacture. The structure includes a cavity formed in a substrate material and which has a curvature at its upper end. The cavity is covered with epitaxial material that has an upper planar surface.

Sealed cavity structures with a planar surface

Fabrication methods and device structures for a heterojunction bipolar transistor. A trench isolation region is formed that surrounds an active region of semiconductor material, a collector is formed in the active region, and a base layer is deposited that includes a first section over the trench isolation region, a second section over the active region, and a third section over the active region that connects the first section and the second section. An emitter is arranged over the second section of the base layer, and an extrinsic base layer is arranged over the first section of the base layer and the third section of the base layer. The extrinsic base layer includes a first section containing polycrystalline semiconductor material and a second section containing single-crystal semiconductor material. The first and second sections of the extrinsic base layer intersect along an interface that extends over the trench isolation region.

Heterojunction bipolar transistors with an inverted crystalline boundary in the base layer

Structures that integrate airgaps with a field-effect transistor and methods for forming a field-effect transistor with integrated airgaps. A first semiconductor layer is formed on a substrate, and a second semiconductor layer is formed over the first semiconductor layer. A source/drain region of a field-effect transistor is formed in the second semiconductor layer. An airgap is located in the first semiconductor layer, The airgap is arranged in a vertical direction between the source/drain region and the substrate.

Field-effect transistors with airgaps

Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both metal material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam.

Growing community of inventors

Colchester, VT, United States of America

Cameron E Luce