Lsi Corporation

Agere Systems Inc.

Avago Technologies General IP (singapore) Pte. Ltd.

Avago Technologies International Sales Pte. Limited

Cameron Carroll Rabe

Jason P Brenden

Michael John O'Brien

Jeffrey A Gleason

Scott M O'Brien

John D Leighton

Hao Fang

Carl F Elliott

Robert Wimmer

Hong Jiang

Ross Wilson

David W Kelly

Peter John Windler

Anamul Hoque

Paul Mazur

Andrew Krebs

Joseph D Stenger

Brad Anthony Natzke

Nameeta Krenz

Jason A Christianson

Bruce Alexander Wilson

Jason S Goldberg

Boris Livshitz

Jaydip Bhaumik

Scott O'Brien

Arvind Reddy Aemireddy

Xuemin Yang

Gang Chen

Paul Mark Mazur

Junqi Hua

A module including first and second variable inductances. The first variable inductance is electrically connected to a pair of nodes in a first half-circuit. One of the nodes in the first half-circuit is a first connection terminal. The second variable inductance is electrically connected to a pair of nodes in a second half-circuit. One of the nodes in the second half-circuit is a second connection terminal. The first half-circuit receives a flow of current in response to the second half-circuit supplying the current to the load in a flow direction from a load through the first connection terminal. The second half-circuit is configured to receive the flow of the current in response to the first half-circuit supplying the current to the load in a direction opposite to the flow direction from the load through the second connection terminal.

Switchable inductor for boost or matching optimization

A storage system includes a magnetic write head, a magnetic storage medium, a channel circuit comprising a write data output, wherein the channel circuit is operable to process write data to be recorded on the magnetic storage medium by the magnetic write head, and a preamplifier operable to receive the write data from the channel circuit, wherein the preamplifier comprises a number of register pages configured to store pattern dependent write current characteristics for a variety of magnet lengths, and wherein the preamplifier is operable to retrieve the write current characteristics based on magnet lengths and to record data bits on the magnetic storage medium using the write current characteristics.

Magnetic recording system using pattern dependent writer having register pages for storing write currents

A method for reducing common-mode disturbances during power-on and power-off modal transitions in a current driver includes providing a programmable current source operative to generate a current having a controllable rise-time and controlling the programmable current source such that a rise-time of the current generated by the current driver is set to a first rise-time value during power-on and power-off modes of operation and is set to a second rise-time value during polarity transitions in a data mode of operation of the current driver, the first rise-time value being greater than the second rise-time value.

Mitigation of common mode disturbances in an H-bridge driver

Amplifier architectures are provided for current sensing applications. An amplifier includes a load device, an operational amplifier, a current source, and a bipolar transistor. The operational amplifier has a first input terminal connected to a first input node that receives an input current, and a second input terminal connected to a second input node that receives a reference voltage. The current source is connected to an output of the operational amplifier. The operational amplifier, the current source, and the bipolar transistor form a feedback loop that generates and maintains a bias voltage on the first input node based on the reference voltage applied to the second input node. The bipolar transistor amplifies the input current received on the first input node, and generates an amplified input current. The load device converts the amplified input current to an output voltage, wherein the output voltage is used to sense the input current.

Analog tunneling current sensors for use with disk drive storage devices

The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for synchronizing operations in a data storage system.

Systems and methods for timing control in a data processing system

A laser driver apparatus, system, and method include a single laser driver. One or more threshold levels and one or more undershoot levels can be digitally combined into a single output with respect to the single laser driver to reduce the output capacitance of the single laser driver and minimize circuit power, resulting in a faster and higher fidelity signal thereof. A decoder (e.g., thermometer decoding) can also be provided, wherein the threshold level(s) and the undershoot level(s) are thermometer decoded via the decoder.

Shared threshold/undershoot laser output driver

A hard disk drive or other storage device comprises a storage medium, a write head, and control circuitry coupled to the write head. The control circuitry comprises a write driver configured to generate a write signal comprising write pulses responsive to write data, and a driver controller configured to adjust overshoot amplitudes of respective ones of the write pulses utilizing a segmented digital-to-analog converter. The overshoot amplitudes are adjusted by detecting patterns in the write data, decoding a first portion of a base overshoot value to identify a corresponding number of base overshoot segments, combining the base overshoot value and a differential overshoot value, decoding a first portion of the combined base overshoot and differential overshoot values to identify a corresponding number of enhanced overshoot segments, and selecting between the number of base overshoot segments and the number of enhanced overshoot segments responsive to detection of a particular pattern.

Storage device with driver controller providing pattern-dependent write functionality

A driver circuit configured to generate a drive signal for an optical source comprises an overshoot controller that provides an amount of overshoot for a given logic state of the drive signal as a function of a duration of at least one previous logic state of the drive signal. The drive signal may alternate between a first logic state associated with a first operating mode of the optical source and a second logic state associated with a second operating mode of the optical source. The overshoot controller may be configured to provide amounts of overshoot for respective instances of the first logic state that are proportional to the durations of their respective immediately preceding second logic states. The driver circuit may be implemented in a heat-assisted magnetic recording system in which the optical source alternates between on and off states associated with respective magnetic write and magnetic read modes.

Optical source driver circuit having overshoot controller

A hard disk drive or other disk-based storage device comprises a storage disk, a read/write head configured to read data from and write data to the disk, and control circuitry coupled to or otherwise associated with the read/write head. The control circuitry comprises a write driver configured to generate a write signal for data to be written to the storage disk, and a multiple-slope transition controller associated with the write driver and configured to control a data transition in the write signal such that the data transition comprises at least two different segments each having a different slope, with the transition controller comprising separate slope control mechanisms for each of the segments. By way of example, the data transition may comprise a dual-slope transition having first and second segments arranged sequentially between a start point and an end point of the data transition.

Storage device having write signal with multiple-slope data transition

Interface circuitry of a storage device or other type of processing device comprises at least one data path, and an adaptive power supply configured to provide a variable supply voltage to the data path. The adaptive power supply comprises a reference voltage circuit having a plurality of field effect transistors collectively configured to provide a variable reference voltage, with different ones of the field effect transistors being biased into different operating regions. For example, a first subset of the field effect transistors may each be biased into a linear region such that the variable reference voltage tracks variations in on-resistance of one or more corresponding field effect transistors of the data path, and a second subset of the field effect transistors may each be biased into a saturation region such that the variable reference voltage tracks variations in threshold voltage of the corresponding field effect transistors of the data path.

Reference voltage circuit for adaptive power supply

Electronic circuitry and techniques are disclosed for controlling one or more timing parameters associated with a circuit that converts a signal of a first type to a signal of a second type. For example, the converter circuit may convert a differential digital logic signal, such as a current mode logic (CML) signal, to a complementary metal oxide semiconductor (CMOS) signal. For example, apparatus for converting a first type of signal to a second type of signal comprises the following circuitry. First circuitry is configured for generating a first pair of CMOS signals in response to a differential digital logic signal, the first pair of CMOS signals comprising a first CMOS signal having a first polarity and a second CMOS signal having a second polarity. Second circuitry is configured for adjusting, with respect to the first pair of CMOS signals, a transition time of one of the first CMOS signal and the second CMOS signal relative to a transition time of another of the first CMOS signal and the second CMOS signal.

Tuning high-side and low-side CMOS data-paths in CML-to-CMOS signal converter

An apparatus and method for controlling the common mode voltage across a data storage device write head. The write current is supplied by a first plurality of parallel current sources each independently activated to limit the common mode voltage generated across the write head. A plurality of parallel resistive elements responsive to current supplied by a second plurality of parallel current sources bias an output transistor that further controls the write current. Each of the plurality of parallel resistive elements and each of the second plurality of parallel current sources is also independently activated to limiting the common mode voltage generated across the write head.

Apparatus and method for controlling common mode voltage of a disk drive write head

An apparatus and method for providing electrostatic discharge protection for a disc drive read head. A pair of depletion mode MOSFETS, and a fuse associated with each are disposed between the read head output terminals. The MOSFETS are controlled to an 'off' state for testing the preamplifier prior to assembly of the read head. After assembly of the head, a second pair of MOSFETS is gated to an 'on' state to open the fuses and thus permit normal operation of the read head.

Method and apparatus for protecting magnetoresistive heads from electrostatic discharge

An impedance matched write circuit is provided that shunts one or more matching resistors. The impedance matched write circuit includes an interconnect for connecting to a write head and at least one resistor between a control voltage and the interconnect for impedance matching to the interconnect. A transistor can be connected across the resistor to shunt current that would otherwise pass through the resistor during an overshoot mode. The transistor may be a PMOS transistor or a combination of PMOS and NMOS transistors. A gate voltage of the transistor is controlled by a source such that the transistor is turned on in an overshoot mode and turned off during a steady state mode.

Growing community of inventors

Inver Grove Heights, MN, United States of America

Cameron Carroll Rabe