Intel Corporation

Hewlett-packard Development Company, L.p.

Cameron B McNairy

Quinn W Merrell

Piyush N Desai

Ayman G Abdo

Jenna S Mayfield

Mohan J Kumar

Sujat Jamil

James B Crossland

Ashok Raj

Kevin Safford

Theodros Yigzaw

Jose Andy Vargas

Ronny Lee Arnold

Benjamin James Patella

Don Soltis

Eric Gouldey

Anil Agrawal

William G Auld

Anthony E Luck

David Heckman

Mark Millican

Scott Hoyt

A processor includes a logic to determine an error condition reported in an error bank. The error bank is communicatively coupled to the processor and is associated with logical processors of the processor. The processor includes another logic to generate an interrupt indicating the error condition. The processor includes yet another logic to selectively send the interrupt to a single one of the logical processors associated with the error bank.

Instruction and logic for machine checking communication

In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing an error framework for a microprocessor and for a system having such a microprocessor. The error framework may alternatively be implemented by a hardware component, such as a peripheral device for integration into a system. In one embodiment, an error framework of a microprocessor or a hardware component includes an error detection unit to capture an error within the hardware component; a state detection unit to capture error context information when the error is detected within the hardware component; an error event definition unit to define a unique error event representing a combination of the error and the error context information; and a configuration unit to define an error event response based on the unique error event. The error context information may include, for example, a known state of a system at the time the error occurs or a known state of the hardware component or microprocessor within which the error is detected at the time the error occurs.

Error framework for a microprocesor and system

Embodiments of a system and method for triggering an event in a hardware abstraction layer (HAL) are generally described herein. In some embodiments, the HAL can include unarchitected hardware or software that can be used to, for example, facilitate instruction emulation and debug; enable protection of model specific resources, instructions, and behaviors; redirect, resteer, or substitute instructions; and provide a framework for additional capabilities and features.

Technology abstraction layer

A method for detecting errors in a processing device is disclosed. A data source unit of a processing device transmits data and a qualifier synchronously with the data, the qualifier to indicate the data is uncorrectable. At least one intermediate functional unit in the processing device receives the data and the qualifier. The at least one intermediate functional unit detects the data is uncorrectable based on the qualifier. The at least one intermediate functional unit transmits, without using, the data and the qualifier synchronously with the data to a data consumer unit of the processing device. The data consumer unit receives the data and the qualifier. The data consumer unit detects the data is uncorrectable based on the qualifier. The data consumer unit maintains, without using the data and the qualifier.

Fault handling at a transaction level by employing a token and a source-to-destination paradigm in a processor-based system

Elements of a computer system are tested by generating harassing transactions on a bus. A first transaction is detected on the bus. The first transaction including a first data request to a first address. In response to and based upon detecting the first address, a second data request is generated to a second address. The second data request is issued on the bus as a second transaction while the first transaction is pending on the bus.

Microprocessor design support for computer system and platform validation

Cache coherency is maintained between the dedicated caches of a chip multiprocessor by writing back data from one dedicated cache to another without routing the data off-chip. Various specific embodiments are described, using write buffers, fill buffers, and multiplexers, respectively, to achieve the on-chip transfer of data between dedicated caches.

Transfer of cache lines on-chip between processing cores in a multi-core system

Parity and mask bit(s) are stored in a random access memory (RAM) that is coupled to a CAM. This CAM may be part of a TLB. The parity and mask bits(s) are stored in conjunction with the CAM entry write. Upon a CAM query match, the reference parity bit(s) and mask bit(s) stored at the address output by the CAM are output from the RAM. These reference parity bit(s) are compared to parity bit(s) generated from a query data value that is masked by the retrieved mask bit(s). In the absence of a CAM or RAM bit error, the reference parity bit(s) from the RAM and the parity bit(s) generated from the masked query data will match. If a CAM or RAM bit error occurred, these two sets of parity bit(s) will not match and thus an error will be detected. This error may be used as an indication that a false CAM match has occurred.

Detection of bit errors in maskable content addressable memories

A validation FUB is a hardware system within the agent that can place a computer system in a stress condition. A validation FUB may monitor transactions posted on an external bus and generate other transactions in response to the monitored transactions. The validation FUB may be a programmable element whose response may be defined by an external input. Accordingly, the validation FUB may test a wide variety of system events.

Growing community of inventors

Windsor, CO, United States of America

Cameron B McNairy