Credo Technology Group Limited

Calvin Xiong Fang

Haoli Qian

William J Brennan

Ashwin Upadhya

Jeffrey Twombly

Active Ethernet cables that provide data path redundancy. One illustrative cable embodiment includes a first connector connected to each of a second and third connectors, the first connector including a multiplexer that couples a data stream from a selectable one of the second and third connectors to an output of the first connector. One illustrative method embodiment includes: producing from an output of a first connector a data stream from a currently selected one of multiple redundant connectors; monitoring the data stream for a fault associated with the currently selected one of multiple redundant connectors; and responsive to detecting said fault, producing from the output of the first connector a data stream from a different selected one of the multiple redundant connectors.

Active ethernet cable with broadcasting and multiplexing for data path redundancy

An illustrative embodiment of a disclosed physical layer interface device includes: a first transmitter and a first receiver for a primary data path; a second transmitter and a second receiver for a secondary data path; a third transmitter and a third receiver for a non-redundant data path; and a multiplexer. The third receiver is coupled to provide a data stream received from the non-redundant data path concurrently to the first and second transmitters, and the multiplexer provides the third transmitter with a selected one of the data stream received via the primary data path and the data stream received via the secondary data path. Disclosed network switch embodiments employ the illustrative physical layer interface to provide internal or external data path redundancy for traffic handled by the network switch.

Physical layer interface with redundant data paths

Accordingly, an improved interposer connection testing technique is provided, employing parallel pseudo-random bit sequence (PRBS) generators to test all the interconnects in parallel and simultaneously detect any correctable defects. In one embodiment, a microelectronic assembly includes an interposer electrically connected in a flip-chip configuration to an originating IC (integrated circuit) die and to a destination IC die, the substrate having multiple conductive traces for a parallel communications bus between the IC dies. The originating IC die has a first parallel PRBS (pseudo-random binary sequence) generator to drive test PRBSs with different phases in parallel across the interposer traces. The destination IC die has a second parallel PRBS generator to create reference PRBSs with different phases, and a bitwise comparator coupled to receive the test PRBSs from the interposer traces and to compare them to the reference PRBSs to provide concurrent fault monitoring for each of the traces.

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Palo Alto, CA, United States of America

Calvin Xiong Fang