Advanced Micro Devices Corporation

Vlsi Technology, Inc.

Spansion Llc.

Philips Electronics North America Corporation

Koninklijke Philips Corporation N.v.

Cypress Semiconductor Corporation

Philips Semiconductors Inc.

Philips Semiconductor, Inc.

Vlsi Technologies, Inc.

Calvin T Gabriel

Lynne A Okada

Fei Wang

Ramkumar Subramanian

Milind Ganesh Weling

Subhas Bothra

Tammy D Zheng

Ian Robert Harvey

Dipankar Pramanik

Subhash R Nariani

Bhanwar Singh

Angela Tai Hui

Suzette Keefe Pangrle

Xi-Wei Lin

Vivek Jain

Phillip Lawrence Jones

Jie Zheng

Shenqing Fang

Harry Jay Levinson

Kuang-Yeh Chang

Rao Venkateswara Annapragada

Michael N Misheloff

William J Boardman

Suzanne Monsees

David P Chan

Christopher F Lyons

Lu You

Jeffrey Allan Shields

Kuo-Tung Chang

Richard J Huang

Marina V Plat

Mark S Chang

Dawn M Hopper

Ning Cheng

Uzodinma Okoroanyanwu

Alexander H Nickel

Jacob D Haskell

Lei Xue

Huaqiang Wu

Harpreet Kaur Sachar

Minh-Van Ngo

Samit S Sengupta

Jihwan Choi

Hiro Kinoshita

Satyendra S Sethi

Emmanuel De Muizon

Zubin Patel

Edward K Yeh

Linda Leard

Linda A Leard

Mark T Ramsbey

James K Kai

Matthew S Buynoski

Sameer S Haddad

Yu Nan Sun

Scott Allan Bell

Srikanteswara Dakshina-Murthy

Hiroyuki Kinoshita

Amit P Marathe

Unsoon Kim

Chun Chen

Darrell M Erb

Joong Jeon

Bryan K Choo

Kouros Ghandehari

Kuo Tung Chang

Inkuk Kang

Bruno M LaFontaine

Wen Yu

Samuel Vance Dunton

Harlan Lee Sur, Jr

Bruno M La Fontaine

James E Nulty

Ercan Adem

Anna Maria Minvielle

Robert J Chiu

David H Matsumoto

Charles Franklin Drill

David E Henderson

Olivier F Laparra

Henry C Lee

Richard D Russ

Seung-Hyun Rhee

Dimitrios Dimitrelis

Tzu-Yen Hsieh

Teresa A Trowbridge

Winny Stockwell

Ecran Adem

Semiconductor devices and methods of manufacturing such devices are described herein. According to embodiments, the semiconductor device can be made by forming a dielectric layer at a first region and at a second region of a semiconductor substrate. A gate conductor layer is disposed over the dielectric formed in the first and the second regions of the semiconductor substrate, and the second region is masked. A split gate memory cell is formed in the first region of the semiconductor substrate with a first gate length. The first region is then masked, and the second region is etched to define a logic gate that has a second gate length. The first and second gate lengths can be different.

Charge trapping split gate embedded flash memory and associated methods

A method for mitigating line-edge roughness on a semiconductor device. The method includes line-edge roughness mitigation techniques in accordance with embodiments of the present invention. The techniques include: reducing the SiON film thickness below a conventional thickness; increasing the photoresist thickness above a conventional thickness; etching the SiON film with an etch bias power less than a conventional wattage amount with an overetch percentage less than a conventional overetch percentage; removing the SiON film layer immediately after completion of the amorphous carbon film layer etching; and lowering the lower electrode temperature below a conventional temperature.

Line-edge roughness improvement for small pitches

A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal film is deposited over the charge trapping layer to form a thick film on top of the core source/drain region and a pinch off and a void or a narrow channel at the top of the STI trench. An etch is performed on the non-conformal film to open pinch-off or widen the narrow channel in the non-conformal. The trapping layer is then completely or partially etched between the core cells. The non-conformal film is removed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide if the trapping layer is partially etched and thus isolate the trap layer.

Self-aligned patterning method by using non-conformal film and etch for flash memory and other semiconductor applications

Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains one or more charge storage nodes, a first poly gate, a pair of first bit lines, and a pair of second bit lines. The second bit line can be formed at a higher energy level, a higher concentration of dopants, or a combination thereof compared to an energy level and a concentration of dopants of the first bit line.

Use of a polymer spacer and Si trench in a bitline junction of a flash memory cell to improve TPD characteristics

Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications

In fabricating an electronic structure, a substrate is provided, and a first barrier layer is provided on the substrate. A germanium thin film diode is provided on the first barrier layer, and a second barrier layer is provided on the germanium thin film diode. A memory device is provided over and connected to the second barrier layer.

Thin film germanium diode with low reverse breakdown

The present invention discloses a system and method for designing grating structures for use in situ scatterometry during the photolithography process to detect a photoresist defect (e.g., photoresist erosion, pattern collapse or pattern bending). In one embodiment, a grating structure may be designed with a pitch or critical dimensional smaller than the one used for the semiconductor device. The pitch and the critical dimension of the grating structure may be varied. In another embodiment, the present invention provides for a feedback mechanism between the in situ scatterometry process and the photolithography process to provide an early warning of the existence of a photoresist defect. If a defect is detected on the wafer, the wafer may be sent to be re-worked or re-patterned, thereby avoiding scrapping the entire wafer.

Methods for designing grating structures for use in situ scatterometry to detect photoresist defects

Systems and methods are disclosed for testing semiconductors at the wafer level, specifically, systems and methods are disclosed that quantify line-edge roughness in terms of electrical properties and the impact of the line-edge roughness on device reliability and performance. A voltage ramp dielectric breakdown (VRDB) test is used to measure the breakdown voltage of the inter-digitated fingers of a semiconductor device. The distribution of breakdown voltage is used to measure the median breakdown voltage and the outliers which fan the extrinsic tail. Thereby, VRDB is used to quantify the impact LER will have on device reliability and performance. The systems and methods also provide a feedback tool to the fabrication process to control line edge roughness to a desired specification.

Quantifying and predicting the impact of line edge roughness on device reliability and performance

The disclosure provides methods to mitigate and/or eliminate problems associated with removal of carbon-based resists from organic low k dielectrics. The methods include forming an organic low k dielectric layer over a semiconductor substrate, forming a capping layer over the organic low k dielectric layer, forming a silicon-containing resist over the capping layer, patterning the silicon-containing resist layer to expose portions of the capping layer and to form a patterned silicon oxide layer, removing the organic low k dielectric layer to form one or more openings, and removing the patterned silicon oxide layer. The silicon-containing resist facilitates efficient patterning of the organic low k-dielectric layers, and thereby increases the performance and cost-effectiveness of semiconductor devices fabricated using organic low k dielectrics.

Silicon-containing resist to pattern organic low k-dielectrics

Methods for eliminating and/or mitigating bridging and/or leakage caused by the contamination of a dielectric layer with fragments and/or residues of a conductive material are disclosed. The methods involve exposing a semiconductor substrate with a dielectric layer contaminated with fragments and/or residues of conductive materials to one or more conductor and/or dielectric etches. The disclosure by eliminating and/or mitigating metal bridging and/or leakage can provide one or more of the following advantages: high device reliability, decreased manufacturing cost, more efficient metallization, and increased performance.

Metal/oxide etch after polish to prevent bridging between adjacent features of a semiconductor structure

In one embodiment, the present invention relates to a method for increasing the ignition reliability of a plasma in a plasma reactor, the method comprising: supplying a source gas to the plasma reactor, the source gas comprising: (a) at least one reactive compound; and (b) at least one ignition gas, wherein the at least one ignition gas increases the ignitability of the source gas as compared to the ignitability of the source gas lacking the at least one ignition gas.

Method to improve ignition in plasma etching or plasma deposition steps

Systems and methods are described that facilitate verifying that bottom apertures in tapered vias are open and free of obstruction. Scatterometry can be employed to monitor tapered via formation during and/or after a dry etch process on a photoresist bilayer. Information regarding critical dimensions at the bottoms of tapered vias can be analyzed to assess whether bottom apertures exhibit a minimum acceptable diameter that is equal to or greater than a predetermined threshold tolerance. Via apertures with dimensions below the threshold tolerance and/or regions of a wafer evincing unacceptable frequent occurrences of faulty via apertures are considered occluded, or suspect, and a corrective re-etch can be performed thereon.

Using scatterometry to verify contact hole opening during tapered bilayer etch

Methods of making a semiconductor structure are disclosed. A refractory metal layer containing W, TiW, Ta, or TaN and semiconductor layer are formed on a substrate that contains copper in, for example, a via therein. A portion of the refractory metal layer and semiconductor layer is removed by etching using a fluorine-containing compound. By using W, TiW, Ta, or TaN as the refractory metal layer material and employing fluorine-based etching, the copper portion in the substrate is not substantially etched, thus preventing corrosion of the copper portion.

Method of making a semiconductor structure

Growing community of inventors

Cupertino, CA, United States of America

Calvin T Gabriel