Northern Telecom Limited

Ciena Corporation

Sige Semiconductor, Inc.

Calvin Plett

Stanley D Rosenbaum

Naim Ben-Hamida

Sadok Aouini

Mahdi Parvizi

John William Mitchell Rogers

Jacob Pike

Reinhard W Rosch

Tingjun Wen

Matthew Mikkelsen

Zdenek J Holy

A circuit includes a programmable frequency divider which receives a high-speed clock, f, as an input and which provides a modulated reference clock as an output; a Sigma-Delta modulator which receives a Frequency Control Word (FCW) and which is connected to the programmable frequency divider to receive the modulated reference clock as a sample clock and to control an average frequency of the modulated reference clock; and an integer-N Phase Lock Loop (PLL) which receives the modulated reference clock and outputs a clock output.

Fractional frequency synthesis by sigma-delta modulating frequency of a reference clock

A decision feedback equalizer (DFE) comprises four charge-steering (CS) primary latches and four primary taps. Two of the four CS primary latches are driven by complementary in-phase quarter-rate clocks and the other two of the four CS primary latches are driven by complementary quadrature quarter-rate clocks. No element of the DFE is driven by any half-rate clocks. In some implementations, each of the primary latches including a respective differential pair of n-channel output transistors and each primary tap includes a respective differential pair of p-channel input transistors connected via their gate nodes to a respective one of the four CS primary latches. In other implementations, each of the primary latches including a respective differential pair of p-channel input transistors and each primary tap includes a respective differential pair of n-channel output transistors connected via their gate nodes to a respective one of the four CS primary latches.

Quarter-rate charge-steering decision feedback equalizer (DFE)

A decision feedback equalizer (DFE) comprises two charge-steering (CS) input latches driven by complementary &#xbd;-rate clocks, two pairs of CS primary latches, and two pairs of taps. The primary latches are driven by &#xbc;-rate clocks. In a first aspect, each one of the input latches and the primary latches includes a respective differential pair of n-channel output transistors, and each tap includes a respective differential pair of p-channel input transistors. In a second aspect, each one of the input latches and the primary latches includes a respective differential pair of p-channel input transistors, and each tap includes a respective differential pair of n-channel output transistors. In some implementations, no element of any one of the taps is driven by any &#xbd;-rate clock. In some implementations, every switch of at least one of the taps is driven by one of the &#xbc;-rate clocks.

Quarter-rate charge-steering decision feedback equalizer (DFE) taps

With the rising popularity in wireless personal communication systems (PCS), there is a need for low-power, low-cost radio receivers. Low cost can be achieved by integrating the required functions as much as possible, thus minimizing the number of off-chip components. The present invention discloses a novel topology for integrating an image reject filter with a traditional low-noise amplifier (LNA) for use in the front-end of a superheterodyne receiver. Previous topologies employing additional filter stages after the LNA have suffered from poor performance and excessive current consumption. Advantageously, the topology of the present invention requires minimal additional circuitry to perform the filtering function, uses only minimal additional current and does not suffer from the same performance limitations as previous topologies.

On-chip image reject filter

Recent trends have seen the desire for lower and lower supply voltages in radio frequency (RF) components as this leads to lower power consumption and, therefore, longer battery life. As well, lower voltages and less current means that mobile products can be made to require fewer battery cells leading to lighter, more compact devices. The present invention discloses a novel topology for providing a low-voltage voltage-controlled oscillator (VCO). The novel topology is based on the negative transconductance oscillator. However, the novel topology of the invention eliminates transistor 'stacking' in the oscillator circuit, thereby allowing the oscillator circuit to be operated at a supply voltage only slightly higher than the turn-on voltage for a single transistor.

Low voltage voltage-controlled oscillator topology

A typical active impedance line feed circuit includes tip and ring amplifiers being controlled in response to signals at tip and ring voltage taps by control circuit to exhibit a.c. impedance and d.c. resistance characteristics for the purpose of supplying energizing current via tip and ring terminals for tip and ring leads of a two wire communication line. In one example of the active impedance line feed circuit, improved operational tolerance of longitudinal interference and of a ground fault condition is provided by a d.c. amplifier being responsive to voltages at the tip and ring terminals. The circuit is characterized in that an inverting input of the d.c. amplifier is connected via resistors to the tip and ring voltage taps. In operation, the d.c. amplifier provides complete cancellation of all common mode signals at the tip and ring voltage taps and a compensation circuit is also connected between the tip and ring voltage taps and is responsive to the output of the control circuit for compensating for non-symmetrical current, the non-symmetrical current being introduced between the tip and ring voltage taps by normal operation of the control circuit, thereby, a threshold of ground fault current limiting action is substantially constant under all operating conditions. The d.c. amplifier is conveniently manufacturable in integrated circuit technology along with the remaining amplifiers in the active impedance line feed circuit.

Active impedance line feed circuit

An amplifier with double rail output being a switchable to single rail output is provided by power pumping circuitry which is controllable by an error detector to deliver modulated power pulses from a d.c. power source to on-following current steering circuits for coupling to either or both of first and second output terminals. In one embodiment the amplifier is envisaged in an integrated circuit form wherein the current steering circuits are provided by switched voltage multipliers of novel structure so that voltage stress of some capacitive elements is reduced, thereby reducing the area these elements would otherwise occupy in the integrated circuit.

Amplifier with double rail output

Voltage multiplier and voltage multipliers in an amplifier with double

A typical active impedance line feed circuit includes tip and ring amplifiers being controlled to exhibit a.c. impedance and d.c. resistance characteristics for the purpose of supplying energizing current for tip and ring leads of a two wire communication line. Protection from excessive heat generation in an instant of a ground fault on the communication line is provided by a d.c. amplifier having an input resistively connected to the tip and ring leads and an output connected via a resistive unidirectional current path to an input of the ring amplifier. A ground fault occurrence causes the resistive unidirectional current path to become conductive and reduces the current flow in the ring lead by causing the output voltage of the ring amplifier to vary in the direction of ground potential. The output of the d.c. amplifier is also useful for improving circuit tolerance of longitudinal interference.

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Ottawa, Canada

Calvin Plett