Bridgelux Incorporated

Radiant Technologies, Inc.

Other

Avago Technologies Ecbu IP (singapore) Pte. Ltd.

Bae Systems Imaging Solutions Inc.

Permacharge Corporation

Hewlett-packard Company

Agilent Technologies, Inc.

Avago Technologies General IP Pte, Ltd.

Calvin B Ward

Joseph T Evans, Jr

Ghulam Hasnain

Julie Elizabeth Fouquet

Alberto M Magnani

Yan Chai

Daniel Bernardo Roitman

Robert G Hockaday

Christopher R Adams

Kean Loo Keh

Chin Hin Oon

Kay Lichtenwalter

Farn Hin Chen

Seiji Inaoka

Jack E Floegel

A light source that is adapted to replace existing fluorescent tubes in an existing fluorescent light fixture is disclosed. The light source includes a plurality of LEDs mounted on a heat-dissipating structure, first and second plug adapters that mate with the florescent tube connectors of the fluorescent tube the light source is to replace, and a power adapter that converts power from a fluorescent tube ballast presented on the first and second plug adapters to DC power that powers the LEDs. The light source is powered from the output of the existing fluorescent ballast. The light source can utilize the existing metallic enclosure as a heat-radiating surface and/or direct air heat transfer from the surface of the heat-dissipating structure.

LED-based replacement for fluorescent light source

An apparatus for taking moving pictures, a method for taking moving pictures, and a novel pixel sensor array are disclosed. The apparatus includes a rectangular imaging array, a plurality of column processing circuits, and a controller. The rectangular imaging array is characterized by a plurality of rows and columns of UHDR pixel sensors and a plurality of readout lines, and a plurality of row select lines. Each column processing circuit is connected to a corresponding one of the plurality of readout lines. The controller causes the rectangular imaging array to measure a plurality of images of a scene that is illuminated by a pulsating light source characterized by an illumination period and a dark period. Each of the images is generated in a frame period which includes an exposure period and a dead period, the dead period being less than the dark period.

LED flicker mitigation for motion pictures

A LIDAR system and a method for operating a LIDAR system are disclosed. The LIDAR system broadly includes a transmitter that that emits a light pulse in response to a launch signal, a receiver that detects light pulses and determines a time of arrival for each detected light pulse; and a controller that generates an ordered sequence of frames. The controller generates a launch signal at the start of each frame and records information specifying a time of arrival relative to the start time for all light pulses received by the receiver until a stop time. After the stop time, the controller waits for the interframe delay time before generating another launch signal. The interframe delay time is different for each frame in the sequence of frames. The controller determines a distance between the transmitter and an object from the recorded information.

LIDAR system that is resistant to noise caused by nearby LIDAR systems

A memory cell and memories constructed from that memory cell are disclosed. A memory according to the present invention includes a ferroelectric capacitor, a charge source and a read circuit. The charge source receives a data value to be stored in the ferroelectric capacitor. The charge source converts the data value to a remanent charge to be stored in the ferroelectric capacitor and causes that remanent charge to be stored in the ferroelectric capacitor. The read circuit determines a charge stored in the ferroelectric capacitor. The data value has more than three distinct possible states, and the determined charge has more than three determined values. The memory also includes a reset circuit that causes the ferroelectric capacitor to enter a predetermined known reference state of polarization.

CMOS analog memories utilizing ferroelectric capacitors

A ferroelectric memory and a method for operating a ferroelectric memory are disclosed. The ferroelectric memory includes a ferroelectric memory cell having a ferroelectric capacitor characterized by a maximum remanent charge, Q. A write circuit receives a data value having more than two states for storage in the ferroelectric capacitor. The write circuit measures Qfor the ferroelectric capacitor, determines a charge that is a fraction of the measured Qto be stored in the ferroelectric capacitor, the fraction being determined by the data value. The write circuit causes a charge equal to the fraction times Qto be stored in the ferroelectric capacitor. A read circuit determines a value stored in the ferroelectric capacitor by measuring a charge stored in the ferroelectric capacitor, measuring Qfor the ferroelectric capacitor, and determining the data value from the measured charge and the measured Q.

Analog ferroelectric memory with improved temperature range

A ferroelectric memory having a plurality of ferroelectric memory cells, each ferroelectric memory cell including a ferroelectric capacitor is disclosed. The ferroelectric memory includes read and write lines and a plurality of ferroelectric memory cell select buses, one select bus corresponding to each of the ferroelectric memory cells. Each of the ferroelectric memory cells includes first and second gates for connecting the ferroelectric memory cell to the read line and the write line, respectively, in response to signals on the ferroelectric memory cell select bus corresponding to that ferroelectric memory cell. A write circuit causes a charge to be stored in the ferroelectric capacitor of the ferroelectric memory cell currently connected to the write line, the charge having a value determined by a data value having at least three states. A read circuit measures the charge stored in the ferroelectric capacitor of the ferroelectric memory cell currently connected to the read line to generate an output value, the output value corresponding to one of the states.

Analog memories utilizing ferroelectric capacitors

A ferroelectric memory having a plurality of ferroelectric memory cells, each ferroelectric memory cell including a ferroelectric capacitor is disclosed. The ferroelectric memory includes read and write lines and a plurality of ferroelectric memory cell select buses, one select bus corresponding to each of the ferroelectric memory cells. Each of the ferroelectric memory cells includes first and second gates for connecting the ferroelectric memory cell to the read line and the write line, respectively, in response to signals on the ferroelectric memory cell select bus corresponding to that ferroelectric memory cell. A write circuit causes a value determined by a data value having at least three states to be stored in the ferroelectric memory cell currently connected to the write line. A read circuit measures the charge stored in the ferroelectric memory cell currently connected to the read line.

Growing community of inventors

Castro Valley, CA, United States of America

Calvin B Ward