Microchip Technology Inc.

Calum Wilkie

Bryan Kris

Jason Michael Sachs

Igor Wojewoda

Michael I Catherwood

David Mickey

Andreas Reiter

Alex Dumais

Thomas S Spohrer

Mike Catherwood

Dave Mickey

Brian Fall

Jason Tollefson

Vincent Sheard

Ashish Desai

Jim Pepping

An article of manufacture includes a non-transitory machine-readable medium. The medium includes instructions that cause a processor to execute a shift instruction. The shift instruction is to cause a source data in memory to be shifted left or shifted right. The shift instruction is to include a source parameter and a bit size parameter. The processor is to execute the shift instruction through a shift of a first source word of the source data by the bit size parameter to yield a first intermediate word, a shift of a second source word of the source data by the bit size parameter to yield a second intermediate word and a first set of shifted-out bits, and through execution of a logical OR operation on the first intermediate word and the first set of shifted-out bits to yield a first result word.

Multibit shift instruction

An integrated circuit has a master processing core with a central processing unit coupled with a non-volatile memory and a slave processing core operating independently from the master processing core and having a central processing unit coupled with volatile program memory, wherein the master central processing unit is configured to transfer program instructions into the non-volatile memory of the slave processing core and wherein a transfer of the program instructions is performed by executing a dedicated instruction within the central processing unit of the master processing core.

Central processing unit with enhanced instruction set

Apparatus and method for protecting program memory for processing cores in a multi-core integrated circuit

In a debugging method for an integrated circuit device which has multiple processing cores, a debugging breakpoint is activated at a first processor core in the integrated circuit device. Upon activation, the debugging breakpoint stops execution of instructions in the first processor core and the debugging breakpoint is communicated to a second processor core in the integrated circuit device.

System and method for generating cross-core breakpoints in a multi-core microcontroller

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Chandler, AZ, United States of America

Calum Wilkie