Honeywell Information Systems Italia

Honeywell Information Systems Inc.

Bull Hn Information Systems Italia S.p.a.

Calogero Mantellina

Daniele Zanzottera

Angelo Casamatta

Claudio Gentili

Alessandro Scotti

Roberto Trivella

Andrea Quadraruopolo

Marco Gelmetti

In a multiprocessor system having global data replication in each of the local memories, each associated with one of the processors, the global data allocation in the several local memories is performed by translating global data logical addresses into addresses conventionally defined as real, the translation being performed by a first translation unit associated with and managed by the processor which generates the global data. The first translation is followed by the translation of the real address into a physical address generally differing for each local memory and performed by a plurality of translation units, each associated with one of the local memories and managed by the processor associated with that local memory.

Multiprocessor system with global data replication and two levels of

In a data processing system wherein a memory is comprised of an unknown plurality of memory blocks of a basic capacity, arranged in an unknown plurality of modules which have an unknown capacity multiple of the basic capacity, a method addresses the memory location which involves the selection of the module containing such locations by use of a directory having a plurality of addressable locations. The initial loading of the directory with codes corresponding to the real constituent of the memory is performed by writing into the directory locations a binary code assigning the related memory blocks to a hypothetical first module, writing test codes into memory locations each belonging to a different block, reading out the contents of the same memory locations and comparing such contents with the test codes to determine if a first module is present and if such memory locations and the pertaining blocks belong to the first module, writing into the directory locations whose related memory block do not belong to the first module a binary code assigning the related memory blocks to a hypothetical second module, writing test codes into memory locations each belonging to a different block assigned to the second module, reading out the contents of the same memory locations and comparing such contents with the test codes to determine if a second module is present and if such memory locations and related memory blocks belong to the second module, and repeating the above operations for further subsequent modules.

Memory mapping method in a data processing system

A memory module selection and reconfiguration apparatus in a data processing system wherein a modular working memory formed by a plurality of memory modules sends to a central processing unit information related to the capacities of the constituting modules (M1, M2, M3, M4) during the system initialization. The central unit processes such information and provides memory, via a channel (30), with information representative of the capacity of the first modules (G1), of the sum of the capacities of the first and second module (G2), of the sum of the capacities of the first, second and third module (G3) and so on, up to the total capacity of the working memory. This information is stored into registers (31, 32), each one related to a possible module, of a module selection unit included inside the working memory. When the memory is addressed, the most significant address portion (BA 03-06) is compared simultaneously by several comparators (33, 34, 35, 36), one for each register, with the content of the several registers. The result of the comparison from the comparators are applied to a decoder (37) which generates signals selecting one among the several memory modules.

Memory module selection and reconfiguration apparatus in a data

A digital timing unit for timing a data processing system or units thereof, wherein the output signals of a shift register are applied to a plurality of EXCLUSIVE OR gates (G.sub.1) . . . (G.sub.n). The shift register is activated from a known state so that an electric transition signal is shifted through the register cells. A timing cycle is thus defined which is utilized to set the register in a second known state. Feedback and control logic are provided for activating the register independently of its state and keeping it in the state occurring at the end of a timing cycle until a new start signal is received. Shifting of the register is caused by timing pulses generated by an oscillator (1). The timing signals generated by the timing unit and present on the output terminals of the EXCLUSIVE OR may be modified, as to the length, by changing the oscillator period and/or the connection between the EXCLUSIVE OR inputs and the outputs of the shift register.

Digital timing unit

A memory system wherein data is stored along with a SEC-DED error detecting and correcting code. Means are provided for selecting either a direct readout path for data from the memory when no readout errors have been detected for the memory address being accessed, or an alternate readout path including circuits for checking and correcting errors when an error condition has been detected. An auxiliary memory is provided for storing error flag bits indicating memory zones which have produced erroneous readouts, whereby the system is controlled such that high speed direct read cycles are executed for no-error memory zones and optimum memory accessing time is achieved without sacrificing the reliability achieved through use of the error correcting codes.

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Cerro Maggiore, Italy

Calogero Mantellina