Cypress Semiconductor Corporation

Caleb Chan

Richard L Kapusta

A programmable logic device includes a plurality of clusters of logic elements. Each of the clusters may include a respective programmable interconnect matrix with each of the logic blocks of each cluster being coupled to the respective programmable interconnect matrix of the cluster. Each of the clusters may be symmetrically coupled to a row and a column of a global routing matrix. The row and the column of the global routing matrix may themselves be symmetrical and each row and/or column may be coupled to an input/output cell of the programmable logic device. The global routing matrix may comprise a plurality of programmable interconnections. In a further embodiment, a symmetrical input/output scheme for a programmable logic device may include a first level routing architecture configured to provide limited intercommunication between a first cluster of logic blocks and a second cluster of logic blocks and a second level routing architecture configured to provide intercommunication between logic blocks within the first cluster. The second level routing architecture being symmetrically coupled to the first level routing architecture at two points of the first cluster. The symmetrical input/output scheme may have the second level routing architecture coupled to the first level routing architecture through a programmable interconnect matrix. The first level routing architecture may further comprise a non-segmented routing matrix which may be symmetrical and which may be laid out as a row and column routing matrix.

Symmetric logic block input/output scheme

A scalable routing architecture for high density programmable logic devices involves the utilization of a two-dimensional network of non-segmented routing channels to serve as global interconnects between clusters of logic blocks. Each cluster of logic blocks is a CPLD-like structure which includes a number of logic blocks connected together by a local interconnect. Logic signals that need to enter a cluster, either from an I/O pin or from another logic block of another cluster, do so by traversing from those sources though a channel interconnect. Similarly, logic signals produced by a cluster can be routed to an I/O pin or to another logic block of another cluster across one of the channels. A switch matrix is implemented at intersections between the channels to allow logic signals to be transferred between rows and columns of the channels.

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Sunnyvale, CA, United States of America

Caleb Chan