Zenith Electronics Corporation

Ikadega, Inc.

Other

Caitlin B Bestler

Khosro M Rabii

Mack S Daily

Harry A Hartley, Iii

Robert C Phillips

Shu-Yuan V Yang

Harry A Hartley

Richard W Citta

Michael E Long

Richard G Merrell

Frederick H Auld, Jr

Larry K Moreland

Rueen-Guang Shyu

A distributed multiprocessor server system and a set of steps performed by the server system are disclosed that facilitate efficient handling of a potentially large workload arising from request messages received from users via a communicatively coupled network link. Workload requests are initially received by a default processor. The default processor redirects at least a portion of the workload request, based upon the type of request, to a specialized processor in a set of special purpose handle processors. Once delegated by a default processor, the request (or a portion thereof) is completed by the specialized handler processor to which the request was delegated. Communications thereafter proceed between the handler processor and a network interface without passing through the default processor.

Network server card and method for handling requests received via a network interface

An information distribution system with an architecture that facilitates efficient distribution of a plurality of information asset data to a plurality of different requesting users substantially simultaneously. Fundamental components of the system include a plurality of mass storage devices that store information assets, mass storage device interface units, a switching unit, a centralized control unit and a gateway to the users. Information transfer between various components of the system is accomplished through a plurality of communication channels according to a circuit switching protocol. According to one embodiment of the invention, a plurality of communication channels are provided between the mass storage devices and the switching unit such that information asset data may be transferred, in substantially a single format and according to substantially a single protocol, from the mass storage devices directly through the switch and to the requesting user.

Information distribution system and method

A subscriber terminal includes a digital conditional access module receiving a transport bitstream comprising a plurality of multiplexed conditional access and product packets. Selected ones of the conditional access packets are addressed to respective terminals and include an encrypted new decryption key code, an encrypted authorization bit map and an authorization list range delete code. The conditional access packets are decrypted by the conditional access modules of respective addressed terminals, the decrypted new decryption key code being stored for subsequent use by the conditional access module, the decrypted authorization bit map being used to refresh the authorization bit map memory of the module and the decrypted delete code being used to delete a specified range of authorization codes from the authorization list memory of the module.

System for updating an authorization memory

A television cable system includes a headend and a decoder coupled by an in-band communication link and an out of band communication link. The headend controller includes conventional transmission systems for providing a plurality of program channels to the decoder via the in-band communication link. In addition, the headend system includes a plurality of controller inputs which provide data to a download executive circuit which in turn organizes data and transfer it to a transmitter coupled to the out of band data link. Within the decoder, a pair of processors are operative via a communication link therebetween. One processor is of predefine capability and is used to operate a user keyboard as well as conventional tuning and signal processing and descrambling systems to provide television display. The remaining processor includes a memory manager coupled to an out of band transmission receiver which receives downloaded interpretive execution data. The decoder further includes a program memory and interpreter circuit operatively coupled to the memory manager. Downloaded data is presented to the interpreter by the dialogue processor which receives instructions in response from the interpreter to execute a particular instruction set or sequence group within the downloaded program. All instruction sets or sequence groups within the downloaded program are free of loops or branch backward instructions to avoid lockout problems.

System for cable communication wherein interpretively coded data

A hybrid analog/digital STB includes a tuner supplying respective analog and digital television signal processing paths. The analog processing path provides demodulated composite analog video and audio signals and the digital processing path provides demodulated component digital video and audio signals. The demodulated analog and video signals are combined in composite or component form to achieve various desirable effects in a highly flexible system architecture. OSD and display map normalization functions are also integrated within the system architecture.

Hybrid analog/digital STB

A television cable system includes a headend and a decoder coupled by an in-band communication link and an out of band communication link. The headend controller includes conventional transmission systems for providing a plurality of program channels to the decoder via the in-band communication link. In addition, the headend system includes a plurality of controller inputs which provide data to a download executive circuit which in turn organizes data and transfer it to a transmitter coupled to the out of band data link. Within the decoder, a pair of processors are operative via a communication link therebetween. One processor is of predefine capability and is used to operate a user keyboard as well as conventional tuning and signal processing and descrambling systems to provide television display. The remaining processor includes a memory manager coupled to an out of band transmission receiver which receives downloaded interpretive execution data. The decoder further includes a program memory and interpreter circuit operatively coupled to the memory manager. Downloaded data is presented to the interpreter by the dialogue processor which receives instructions in response from the interpreter to execute a particular instruction set or sequence group within the stored program. All instruction sets or sequence groups within the stored program are free of loops or branch backward instructions to avoid lockout problems.

Television distribution system having virtual memory downloading

A combined condition access and transport demultiplexer circuit comprises a decryption device receiving a demodulated transport bitstream including a plurality of multiplexed conditional access (CA) and product (e.g. video, audio and data) packets, each CA packet being identified by a CA PID and each product packet by a respective product PID. A comparator is provided for comparing the PID of each received packet with a plurality of stored PID values representing the CA PID and selected product PID's. A routing manager is responsive to the comparator for routing received CA packets from the decryption device to a conditional access circuit which controls the decryption device and for routing received product packets to appropriate output ports for further processing.

Combined DCAM and transport demultiplexer

A digital conditional access module for a subscriber terminal comprises a decryption device including at least one PID register and an associated countdown register. The decryption device is enabled for decrypting received product packets having a PID matching a PID stored in the PID register so long as the associated countdown register is characterized by a non-zero value. Decryption of a product packet results in the countdown register being decremented by a selected factor, the countdown register being prevented from assuming a zero value by setting its contents to a selected value in response to a received conditional access packet containing a PID matching the PID stored in the PID register. The selected value to which the countdown register is set may also be contained within the received conditional access packet.

Countdown system for conditional access module

Each of a plurality of terminals in a two-way communications system includes a series of counters establishing a plurality of time slots synchronized to a downstream reference parameter. Upstream transmissions are effected by each terminal in one or more of the time slots which are defined by a downloaded message as comprising either a reserved slot or a contention slot. The downloaded message, which may also establish terminal transmission power levels and retransmission backoff algorithms for contention time slots, is derived on the basis of the population of subscriber terminals and the usage of the upstream channel.

Upstream data transmission system with downloadable transmission

A cable television upstream data transmission system provides a plurality of uniquely assignable time slots for use by subscriber terminals in upstream data transmission. The unique assignment of time slots provides guaranteed access for each subscriber terminal during its time slot. The width and number of time slots are controlled by a pair of programmable values which may be downloaded from the cable system headend to accommodate dynamic changes of the cable system. A transmission modulator used within the subscriber terminal produces an upstream transmission carrier having a frequency locked to a common network reference signal such as the system symbol clock. The frequency of the carrier signal produced by the transmission modulator is programmably controlled by a plurality of program values which are selected to provide frequency and phase lock of the modulator's carrier to the symbol clock network reference signal.

Transmission modulator for cable television upstream data transmission

A cable television upstream data transmission system provides a plurality of time slots synchronized to the downstream symbol clock for use by subscriber terminals in upstream data transmission. The width and number of time slots are controlled by a pair of downloadable values to accommodate dynamic changes of the cable system. A transmission modulator used within the subscriber terminal produces an upstream transmission carrier having a frequency locked to the symbol clock. The frequency of the carrier signal produced by the transmission modulator is programmably controlled by a plurality of program values which are selected to provide frequency and phase lock of the modulator's carrier to the symbol clock.

Upstream data transmission system for cable television

A microprocessor communication system couples two microprocessors over a bus comprising a bidirectional data line, a bidirectional sync line and a pair of clock lines. A toggled clock signal serves as a control signal. Each microprocessor outputs data to the data and sync lines and monitors its incoming clock line. When a toggled clock signal is sensed, the receiving microprocessor, when its priorities permit, takes control of the bus and stops outputting data to the data and sync lines. It then detects the incoming data and when incoming data reception is completed, the microprocessor outputs new information to the data and sync lines and toggles its output clock line to signal to the other microprocessor that control of the bus has been relinquished. With the system, the microprocessors operate without the constraints of predetermined time intervals in which to output data or to receive data.

Controlling data transfer between two microprocessors by receiving input

Upstream transmissions in a two-way communications network are effected from subscriber terminals in upstream packets having one of a plurality of different separately acknowledgeable acknowledgment tags. Downstream acknowledgments of upstream messages are contained in CA packets multiplexed with product packets to form a transport bitstream. The transport bitstream is applied to a digital conditional access module (DCAM) in the terminal which is controlled by the conditional access data bits of the CA packets. The DCAM includes a status register for storing the acknowledgment bits of the CA packets, which bits are coupled by a microprocessor for controlling the upstream transmitter.

Upstream transmission using multiple transmission tags and downstream

A method of operating a cable system having premium channel encoders and dedicated smart pay per view encoders, each associated with an individual channel. The pay per view encoders are provided with the addresses of certain subscriber stations that have been approved to decode pay per view events on the associated channels. These certain subscriber stations are addressed on a priority basis by the pay per view encoder handling the pay per view event to set their authorization memories to decode the pay per view event. The authorization memories are updated by RAM groups of five program tags. All of the PPV encoders are assigned to the same RAM group so that in updating authorization memories, the authorization of a subscriber station memory for another pay per view event is not altered. The authorization process is rapidly accomplished and is repeated for a period of time after commencement of the pay per view event. The certain subscriber stations are immediately deauthorized by the same pay per view encoder at the end of the pay per view event.

Method of operating a pay per view television system

A cable television system includes a headend unit having a plurality of program signal sources, encoders, scrambling circuits, and channel modulators for producing a plurality of program channels modulated at a corresponding plurality of cable system carrier frequencies. An address computer within the headend unit is operative upon the encoders to provide the insertion of a message packet within the vertical blanking interval of the program signals. The scrambler circuits render the program signal unviewable by conventional television receivers. A cable system decoder is coupled to the headend by a cable and includes a conventional tuner, intermediate frequency amplifier and detector. A decoder processor is coupled to a channel selection input and to the tuner to provide channel selection in accordance with a user input. The decoder processor examines the message packet during the vertical blanking interval to determine authorization of the decoder to display the received program channel. A descrambler is coupled to the processor and the tuner IF and detector to descramble the program signal if authorization is detected. A modulator modulates the descrambled signal upon a fixed channel carrier for application to a conventional television receiver.

Growing community of inventors

Chicago, IL, United States of America

Caitlin B Bestler