Cadence Design Systems, Inc.

Jasper Design Automation, Inc.

Caio Araújo Teixeira Campos

Lawrence Loh

Victor Markus Purri

Claudionor Jose Nunes Coelho

Magnus Björk

A formal verification approach verifies data access and data propagation paths in a circuit design by proving the unreachability of path cover properties of the circuit design. A security path verification system receives an original circuit model of a circuit design, along with parameters identifying a first location within the circuit design that is a source of tainted data and a second location within the circuit design that is coupled to the first location. The security path verification system also receives a selection of portions of the circuit design to be excluded from the verification analysis. Using an abstracted version of the exclude portions, the security verification system generates a second circuit model of the circuit design for use in determining whether the tainted data can reach the second location from the first location within the circuit design.

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Austin, TX, United States of America

Caio Araújo Teixeira Campos