Cadence Design Systems, Inc.

Caio Alves Furtado

Mirlaine Aparecida Crepalde

Raquel Lara Dos Santos Pereira

Breno Augusto Dias Vitorino

Rodrigo Da Silva Mantini Viana

Luis Humberto Rezende Barbosa

Lucas Duarte Prates

The present disclosure relates to a method for use in the formal verification of an electronic circuit. Embodiments may include receiving, using a processor, a portion of an electronic circuit design and analyzing a syntactic structure of a string associated with the electronic circuit design. Embodiments may also include generating a parse tree, based upon, at least in part, the analysis and traversing the parse tree to identify one or more conditional nodes. Embodiments may further include generating a new node for each of the one or more conditional nodes and displaying, at a graphical user interface, a check, at least one of the one or more conditional nodes or the new node prior to performing either register-transfer-level RTL synthesis or final synthesis.

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Belo Horizonte, Belize

Caio Alves Furtado