Raytheon Company

Caesar J Favaloro

Robert G Curtis

Nathan A Liskov

Richard G Cease

Gregory L Pence

James G Hackendorf

A circuit and method for generating a substantially smooth clock for clocking asynchronous data to a user device. Incoming asynchronous data is stored in an elastic buffer such as a first-in first-out memory. Periodically, an output identifiable bit is read into the memory and a multibit digital signal corresponding to the number of output clock pulses for it to be read out is determined. This signal, which corresponds to the occupancy of the first-in first-out memory, is used to generate an analog voltage which controls a voltage controlled oscillator that provides the substantially smooth clock for reading data out of the first-in first-out memory. The control loop causes the long term rate of the smooth clock to be substantially equal to the incoming asynchronous data rate.

Asynchronous data clock generator

An eye opening monitor for a binary waveform such as provided as the video output of a demodulator. At the decision sample time, the video is compared to -V.sub.th and +V.sub.th reference voltages to determine if it falls in the range defined therebetween. If it does, a counter is reset. Because the carry-out pulses of the counter are used to produce -V.sub.th and +V.sub.th, the range defined therebetween is decreased by the additional time required to count to the carry-out after the counter is reset. The loop stabilizes with the range from -V.sub.th and +V.sub.th being quantitatively indicative of the eye opening. A voltage derived from V.sub.th is visually displayed.

Growing community of inventors

Sudbury, MA, United States of America

Caesar J Favaloro