Texas Instruments Corporation

Nantero, Inc.

Other

Texas Tech University System

Fsi Corporation

C Rinn Cleavelin

Thomas Rueckes

Claude Louis Bertin

X M Henry Huang

A Kathleen Hennessey

YouLing Lin

Rajasekar Reddy

Wan S Wong

H Montgomery Manning

Howard V Hastings, Ii

David J McElroy

Manzur Gill

Sung-Wei Lin

Ramakrishna Pattikonda

Zhiqiang (Jeff) Wu

Shaofeng Yu

Feng Gu

Michael Francis Pas

Youling Lin

Robert S Blackwood

Sylvia D Pas

Darlene Hamilton

Veera S Khaja

Rex L Biggerstaff

Kwang-Soo Hahn

L Davis Clements

Ramachandra R Katragadda

Pinar Kinokoglu

Pinar Kinikoglu

Stephen J Demoor

The present disclosure is directed toward carbon based diodes, carbon based resistive change memory elements, resistive change memory having resistive change memory elements and carbon based diodes, methods of making carbon based diodes, methods of making resistive change memory elements having carbon based diodes, and methods of making resistive change memory having resistive change memory elements having carbons based diodes. The carbon based diodes can be any suitable type of diode that can be formed using carbon allotropes, such as semiconducting single wall carbon nanotubes (s-SWCNT), semiconducting Buckminsterfullerenes (such as C60 Buckyballs), or semiconducting graphitic layers (layered graphene). The carbon based diodes can be pn junction diodes, Schottky diodes, other any other type of diode formed using a carbon allotrope. The carbon based diodes can be placed at any level of integration in a three dimensional (3D) electronic device such as integrated with components or wiring layers.

Electrostatic discharge protection devices using carbon-based diodes

Methods for scaling dimensions of resistive change elements, resistive change element arrays of scalable resistive change elements, and sealed resistive change elements are disclosed. According to some aspects of the present disclosure the methods for scaling dimensions of resistive change elements and the resistive change element arrays of scalable resistive change elements reduce the impact of overlapping materials on the switching characteristics of resistive change elements. According to some aspects of the present disclosure the methods for scaling dimensions of resistive change elements include sealing surfaces of resistive change elements. According to some aspects of the present disclosure the methods for scaling dimensions of resistive change elements include forming barriers to copper migration in a copper back end of the line.

Methods of making sealed resistive change elements

Non-linear resistive change memory cells and arrays

Methods for forming crosspoint arrays of resistive change memory cells

Sealed resistive change elements

Resistive change elements incorporating carbon based diode select devices

Resistive change element array using vertically oriented bit lines

Cross point arrays of 1-R nonvolatile resistive change memory cells using continuous nanotube fabrics

Carbon based nonvolatile cross point memory incorporating carbon based diode select devices and MOSFET select devices for memory and logic applications

Methods for adjusting and/or limiting the conductivity range of a nanotube fabric layer are disclosed. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via wet chemistry techniques. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via plasma treatment. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via CVD treatment. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via an inert ion gas implant.

Methods for adjusting the conductivity range of a nanotube fabric layer

A technique is disclosed for increasing the width of a transistor () while the transistor itself may be scaled down. The transistor width () is increased by forming recesses () within shallow trench isolation (STI) regions () adjacent to the transistor (). The recesses () provide an area that wraps around the transistor and thereby increases the width () of the transistor (). This wraparound area provides additional space for dopant atom deposition, which facilitates a reduction in random dopant fluctuation (RDF). In this manner, transistors formed in accordance with one or more aspects of the present invention, may yield improved performance when incorporated into SRAM since the probability that such transistors will be more closely matched is increased.

Method to improve SRAM performance and stability

A method and system for generating and managing a knowledgebase for use in identifying anomalies on a manufactured object, such as a semiconductor wafer, includes measures for adding, deleting, and organizing data from the knowledgebase.

System and method for classifying an anomaly

A system and method allow for associating a descriptive label with an anomaly on a manufactured object, such as a semiconductor wafer. The method includes placing the manufactured device on a moveable stage; capturing and preparing a digital-pixel-based representation of the image; symbolically decomposing the digital-pixel-based representation of the image to create a primitive-based representation of the image; analyzing the primitive-based representation of the image to detect and locate the anomaly; isolating primitives associated with the anomaly; comparing the isolated primitives associated with the anomaly with primitives in a knowledge base to locate a set of primitives in the knowledge base most like the isolated primitives associated with the anomaly; and assigning a label associated with the set of primitives in the knowledge base that was most similar to the isolated primitives associated with the anomaly. Different layers of semiconductor wafer may be analyzed to determine an appropriate label for a defect.

Method and system for identifying defects in a semiconductor

System and method for knowledgebase generation and management

A system and method for repairing a defect on a manufactured object, which may be a semiconductor wafer, uses a computer and a repair tool. The method includes placing the manufactured device on a moveable stage; capturing and preparing a digital-pixel-based representation of the image; symbolically decomposing the digital-pixel-based representation of an image to create a primitive-based representation of the image; analyzing the primitive-based representation of the image to detect and locate an anomaly; isolating primitives associated with the anomaly; comparing the isolated primitives associated with the anomaly with primitives in a knowledgebase to locate a set of primitives in the knowledgebase that are most like the isolated primitives associated with the anomaly; assigning a defect-type label associated with the set of primitives in the knowledge base that was most similar to the isolated primitives associated with the anomaly; and using a repair tool to repair the defect based on defect-type label for the anomaly.

System and method for circuit repair

Growing community of inventors

Lubbock, TX, United States of America

C Rinn Cleavelin