Texas Instruments Corporation

C Matthew Thompson

Byron Lovell Williams

Xiaoju Wu

Taylor R Efland

Louis N Hutter

Han-Tzong Yuan

Jau-Yuann Yang

John P Erdeljac

Alec James Morton

John Kenneth Arch

Jeffrey P Smith

Maxwell Walthour Lippitt, Iii

Erika Leigh Shoemaker

Betty S Mercer

Laurinda W Ng

Mary Ann Murphy

An integrated circuit with transistor regions formed on a substrate. Each transistor region includes a channel region and a terminal region. The channel region is positioned along a traverse dimension, and it includes a channel edge region along a longitudinal dimension. The terminal region is positioned adjacent to the channel region, and it is doped with a first dopant of a first conductivity type. Each transistor region may include an edge block region, which is positioned along the longitudinal dimension and adjacent to the channel edge region. The edge block region is doped with a second dopant of a second conductivity type opposite to the first conductivity type. The channel region doped with a dopant and having a first doping concentration. Each transistor region may include an edge recovery region overlapping with the channel edge region and having a second doping concentration higher than the first doping concentration.

MOSFET transistors with robust subthreshold operations

An embodiment relates generally to a method of forming a capacitor. The method includes depositing a first layer of polysilicon on a substrate and implanting a high dose of implant into the first layer of polysilicon. The method also includes depositing a layer of dielectric over the first layer of polysilicon and depositing a second layer of polysilicon over the layer of dielectric. The method further includes implanting an equivalent concentration of implant in both the first layer of polysilicon into the second layer of polysilicon.

Methods and apparatus for forming a polysilicon capacitor

The present invention provides an interconnect for use in an integrated circuit, a method for manufacturing the interconnect, and a method for manufacturing an integrated circuit including the interconnect. The interconnect (), among other elements, includes a surface conductive lead () located in an opening formed within a protective overcoat (), and a barrier layer () located between the protective overcoat () and the surface conductive lead (), a portion of the barrier layer () forming a skirt () that extends outside a footprint of the surface conductive lead ().

Method for manufacturing an interconnect

A power field effect transistor is disclosed that includes polysilicon gate bodies (,) and (,), which includes platinum silicide contact layers (,) and (,) disposed on the outer surfaces of bodies (,) and (,), respectively. In addition, the device comprises an n&plus;drain region (,) which also has a platinum silicide drain contact layer (,) formed on its outer surface and platinum silicide source contact layers (,) and (,). During formation, sidewall spacers (,) and (,), as well as mask bodies (,) and (,) are used to ensure that platinum silicide layer (,) spaced apart from both gate bodies (,) and (,) and platinum silicide gate contact layers (,) and (,).

Power transistor with silicided gate and contacts

Growing community of inventors

Highland Village, TX, United States of America

C Matthew Thompson