Alcatel Network Systems, Inc.

C Lee Marusik

Edward D Johnson

Brent A Elliott

A self-biased power isolator system is disclosed that provides a fault tolerant power system without the need for auxiliary power. Enhancement-mode MOSFET 120 includes a drain coupled to a first node, a source coupled to a second node, and a gate. Amplifier 50 includes inputs for comparing the voltages from the first and second nodes and an output coupled to the gate of MOSFET 120 by which amplifier 50 controls the state of enhancement-mode MOSFET 120. Amplifier 50 further includes a positive power input coupled to the second node and a negative power input coupled to ground. In one embodiment, the first node is operable to be coupled to a power supply 10 and the second node is operable to be coupled to a load 18. A further embodiment allows the architecture to be replicated, each coupled at the second node to provide an N+1 fault tolerant power system.

Self-biased power isolator system

Magnetic amplifier post regulator (54) includes magnetic amplifier (42) that has a main magnetic amplifier winding, reset transistor (76), error amplifier (58), and auxiliary magnetic amplifier winding (220). Magnetic amplifier (42) controllably blocks a portion of the input voltage N.sub.s /N.sub.p V.sub.IN from winding (30) of transformer (18) in response to a controlled resetting condition and produces therefrom a magnetic amplifier output voltage (v.sub.2). Auxiliary output circuit (14) uses the magnetic amplifier (42) output voltage (v.sub.2) to produce the desired auxiliary output voltage (V.sub.OS). Reset transistor (76) controls reset current to magnetic amplifier (42) in response to an error signal from error amplifier (58). Error amplifier (58) compares auxiliary output voltage (V.sub.OS) to predetermined reference voltage (66) and generates the error signal from the comparison. Auxiliary magnetic amplifier winding (220) has a predetermined number of turns (N.sub.2) on magnetic amplifier (42) and increases the dynamic range of magnetic amplifier post regulator (54) for controlling reset transistor (76) and auxiliary output circuit (14) so that auxiliary output voltage (V.sub.OS) may attain a zero value while reset transistor (76) controls magnetic amplifier (42) in a blocking state (T.sub.B) during the entire on-time (T.sub.ON) of power switch transistor (24) of primary circuit (16).

Method and circuitry for controlling current reset characteristics of a

Start-up control circuit (152) regulates the output voltage (V.sub.OS) of a power supply circuit (150). Magnetic amplifier control circuit (54) includes magnetic amplifier (42) and error detection circuitry (58, 68, and 70). Start-up control circuit (152) includes sensing circuitry (76 and 184) for generating sensing signals in response to voltage levels (V.sub.CC and V.sub.EE) in error detection circuitry (58, 68, and 70). Sensing signals indicate whether error detection circuitry (58, 68, and 70) voltage levels are sufficient to drive magnetic amplifier control circuit (54). Reset circuitry (190 and 192, and 194) associates with the sensing circuitry (76 and 184) for initially resetting magnetic amplifier (42) to prohibit output voltage (V.sub.OS) from power supply circuit (150) when the sensing signals indicate that voltage levels are insufficient for error detection circuitry to drive magnetic amplifier control circuit (54). Reset circuitry (190 192, and 194) further associates with reset control transistor (76) for controllably decreasing the reset of magnetic amplifier (42). Reset circuitry (190, 192, and 194) further associates with magnetic amplifier control circuit (54) for shifting control of magnetic amplifier (42) to magnetic amplifier control circuit (54) as voltage levels increase sufficiently for the error detection circuitry (58, 68, 70) to drive magnetic amplifier control circuit (54).

Method and circuitry for controlling start-up characteristics of a

Two pulse-width modulated power supplies are synchronized to operate at 180.degree. of phase shift to reduce the peak amplitude of the instantaneous current drawn from the DC input bus. The circuit includes means for disabling the synchronization upon detection of an undervoltage fault condition on the output of either supply. This feature allows frequency programming techniques to be used to provide foldback current limiting for either supply without affecting the operation of the other supply.

Switching mode power supplies with controlled synchronization

Overvoltage and component failure protection for redundant current-mode controlled power supplies operating in parallel takes a supply off line when the supply drives the output bus to an overvoltage condition, without removing properly functioning supplies from the bus. The supply is also taken off line when either the error amplifier or the PWM fails.

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McKinney, TX, United States of America

C Lee Marusik