Qualcomm Incorporated

ByungWook Min

Der-Woei Wu

Eugene Robert Worley

Chan Hong Park

An integrated circuit (IC) for compensating for a package inductance is disclosed. A first ground pad is directly connected to an on-chip ground node. A second IC ground pad is connected to the on-chip ground node via a tunable capacitor circuit, where the capacitance of the tunable capacitor circuit resonates with the package inductance at the operating frequency of the IC.

Package inductance compensating tunable capacitor circuit

Improved ESD protection circuits for RFICs requiring both high voltage and high frequency operation is described. A cascode grounded gate snap-back NFET (GGNFET) combined with a precharge circuit and a diode network results in a positive ESD protection clamp with low capacitance and high turn-on voltage. The positive ESD protection clamp provides ESD protection to an IC during a positive voltage ESD pulse. Exemplary embodiments of a negative ESD protection clamp are disclosed where a bias circuit or a charge pump is used in place of the precharge circuit in a manner that allows the combination of the bias circuit or the charge pump together with a diode network and a cascode grounded gate snap-back NFET to provide protection against negative ESD voltage pulses. The combination of a positive and a negative ESD protection clamp provides ESD protection to an IC during either a positive or a negative voltage ESD pulse. Alternate embodiments further reduce the capacitance of the ESD protection circuit by using only a positive ESD clamp to provide ESD protection during a positive ESD pulse while protection for a negative ESD pulse is provided by a discharge path formed by a path of an RF front-end switch coupled to a negative ESD diode.

High voltage, high frequency ESD protection circuit for RF ICs

A mobile communication device comprises a plurality of receivers, a phase detection circuit, and a DC offset calibration circuit. Each receiver comprises a receiver chain and a divide-by-2 circuit that supplies Local Oscillating (LO) signal for the receiver chain. The LO signals leak to each receiver chain and create an undesirable DC offset voltage. The DC offset depends on an LNA gain and a phase relation among the LO leakages. In a first novel aspect, a two-dimensional DC offset calibration (DCOC) table is prepared for each receiver chain. In a second novel aspect, the phase detection circuit detects the phase relation among the LO leakages for each receiver chain. Based on the LNA gain and the detected phase relation of each receiver chain, a DCOC code is selected from a corresponding DCOC table such that the calibration circuit calibrates the DC offset for each receiver effectively and efficiently.

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San Antonio, TX, United States of America

ByungWook Min