Synopsys, Inc.

Byungwook Kim

Weiping Fang

Baribrata Biswas

Beifang Qiu

Himanshu Sharma

Goetz Leonhardt

Kishore Singhal

John R Studders

Yuli Xue

Mahmoud Shahram

Virender Kashyap

Abhishek Khandelwal

Edhi Sutjahjo

Sergey Krasnovsky

Alex Gyure

A computer-implemented method for constructing a design characterized by a double patterning layer is presented. The method includes receiving the design in a memory of the computer when the computer is invoked to construct the design. The method further includes generating, using the computer, a multitude of fill shapes along a multitude of tracks associated with a multitude of net shapes. The multitude of fill shapes and the multitude of net shapes are decomposable into two colors in accordance with a spacing constraint of the double patterning layer.

Constructing fill shapes for double-patterning technology

A computer-implemented method for validating a design characterized by a multi-patterning layer is presented. The method includes receiving the multi-patterning layer in a memory of the computer when the computer is invoked to validate the design. The method further includes correcting, using the computer, a first error in a first shape of the multi-patterning layer in accordance with a first rule thereby forming a corrected layer. The method further includes incrementally validating, using the computer, a first portion of the corrected layer in accordance with the first error and a first connected component of a first graph associated with the multi-patterning layer.

Incremental multi-patterning validation

One embodiment of the present invention provides a system for determining an electrical property for an interconnect layer. During operation, the system receives interconnect technology data which includes nominal parameter values for a first interconnect layer, and parameter-variation values which represent variations in the nominal parameter values due to random process variations. Next, the system receives an interconnect template which describes the geometry of a portion of a second interconnect layer. The system then determines electrical property data for the interconnect template using the interconnect technology data. The electrical property data can include a nominal electrical property value, and sensitivity values which represent the sensitivities of the nominal electrical property value to variations in the nominal parameter values. Next, the system stores the electrical property data and the interconnect technology data in a storage.

Method and apparatus for facilitating variation-aware parasitic extraction

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Los Altos Hills, CA, United States of America

Byungwook Kim