Samsung Electronics Co., Ltd.

Sungkyunkwan University

Byungwook Cho

June-Hee Lee

Bongkyu Kim

Donghyuk Lim

Gun-Il Kang

Junghoon Chun

Youngseob Suh

Subin Yim

A receiving device includes a delay buffer configured to receive an analog signal and output a delayed analog signal, a phase interpolator configured to output a clock signal based on a phase compensation code signal and a reference clock signal, an analog-to-digital converter group configured to output a slope type determination signal indicating a slope of the analog signal based on the analog signal and the delayed analog signal, and a clock data restorer. The clock data restorer is configured to determine a curve type associated with a plurality of digital samples from the analog-to-digital converter group. The clock data restorer also evaluates a timing of the clock signal based on the curve type and the slope type determination signal, and outputs the phase compensation code signal to move the sample timing closer to an optimum timing.

Receiving device and operating method thereof

An apparatus includes an equalization circuit, an error prediction circuit, a sequence estimation circuit, and a selection circuit. The equalization circuit is configured to generate a first data sequence and a first equalized signal from an input signal received through a channel. The error prediction circuit is configured to predict an error based on the first equalized signal when the error is predicted. When the error is predicted, the sequence estimation circuit is configured to generate a second data sequence from the first data sequence and the predicted error. The selection circuit is configured to output the second data sequence when the predicted error is determined to be an actual error and to otherwise output the first data sequence.

Apparatus and method for channel equalization based on error detection

A receiver includes a sampler that samples first voltage levels corresponding to a first logical value of data and second voltage levels corresponding to a second logical value of the data, based on a sampling clock. An equalizer receives and adjusts the first and second voltage levels. A clock and data recovery circuit recovers the sampling clock, based on the first and second voltage levels from the equalizer. An eye opening measurement circuit: (1) tracks a first sigma level by a first step unit depending on upper voltage levels greater than a first reference voltage level among the first voltage levels, (2) tracks a second sigma level by a second step unit depending on lower voltage levels less than a second reference voltage level among the second voltage levels, and (3) calculates a difference between the first sigma level and the second sigma level.

Eye opening measurement circuit calculating difference between sigma levels, receiver including the same, and method for measuring eye opening

An electronic device includes a reception equalizer that performs, a first equalization on a first signal based on a first coefficient, and one or more second equalizations on one or more second signals based on the first coefficient, the one or more second signals being based on a second coefficient associated with one or more characteristics of a transmission equalizer of the external device, and circuitry that iteratively sends control information generated based on the first coefficient to the external device until a termination condition is satisfied with regard to the first coefficient, the control information causing the second coefficient to be increased or decreased, the iteratively sent control information causing a first absolute value of the first coefficient corresponding to a final equalization of the one or more second equalizations to become smaller than a second absolute value of the first coefficient corresponding to the first equalization.

Growing community of inventors

Hwaseong-si, South Korea

Byungwook Cho