Innowireless Co., Ltd.

Byungkwan Jang

Jinsoup Joung

Seunghwan Ji

Kyeongmin Ha

Yonghoon Lim

Junwan Park

An apparatus and a method of compensating for an I/Q imbalance in a direct up-conversion system prevents the performance of the system from being deteriorated by efficiently compensating for an I/Q timing skew, an I/Q phase imbalance, and an I/Q gain imbalance by using a characteristic of an OFDM scheme in an Orthogonal Frequency Domain Multiple (Access) (OFDM(A)) system using a direct up-conversion scheme. According to the apparatus and the method of compensating for an I/Q imbalance in the direct up-conversion system of the present invention, an OFDM(A) system using a direct up-conversion scheme may efficiently compensate for I/Q timing skew, I/Q phase imbalance, and I/Q gain imbalance by using a characteristic of an OFDMA scheme, so that a performance of the system is prevented from being deteriorated.

Apparatus and method of compensating for I/Q imbalance in direct up-conversion system

The present invention relates to an apparatus and a method for eliminating I/Q offset in a receiver of a SC-FDMA system which improves performance of the system by accurate measurement and cancellation of I/Q offset in a receiver of a SC-FDMA system operating in a 3GPP LTE uplink. An apparatus for eliminating I/Q offset in a receiver of the SC-FDMA system constituting the receiver of the SC-FDMA system includes: a linear interpolation channel estimation unit for estimating channel using demodulation reference symbol (DMRS) that is a training sequence (X) corresponding to the discrete Fourier transformed signal (Y) that has passed through frame sync acquisition, frequency compensation and cyclic prefix elimination; a signal regeneration/cancellation unit for calculating I/Q offset (D=Y&#x2212;Y') by subtracting the discrete Fourier transformed signal (Y) from the ideal discrete Fourier transformed signal (Y&#x2032;=H&#x2032;X) generated by using channel coefficient (H&#x2032;), that is an output of the linear interpolation channel estimation unit, and the DMRS that is the training sequence (X); and an I/Q offset measurement/cancellation unit for generating VQ offset-free signal (Y=Y&#x2212;D&#x2032;) by subtracting I/Q offset (D&#x2032;) having corrected phase and power of the VQ offset (D=Y&#x2212;Y&#x2032;) from the discrete Fourier transformed signal (Y).

Apparatus and method for I/Q offset cancellation in SC-FDMA system

Disclosed herein are an apparatus and method for synchronizing a signal analyzer. The apparatus includes an Analog-to-Digital Converter (ADC), a signal storage unit, a trigger signal generation unit, a signal acquisition control unit, a signal analysis unit, and a time error control unit. The ADC converts the input signal into a corresponding digital signal. The signal storage unit stores therein the digital signal received from the ADC. The trigger signal generation unit generates a trigger signal for each predetermined period. the signal acquisition control unit acquires the digital signal from a signal acquisition time point. The signal analysis unit calculates the start position of a frame from the digital signal. The time error control unit calculates a time error between the time point at which each trigger signal is generated and the start position of the digital signal, and sets a subsequent signal acquisition time point based on the calculated time errors.

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Yongin-si, South Korea

Byungkwan Jang