Samsung Electronics Co., Ltd.

Byungki Han

Jaehong Jung

Kyungmin Lee

Seungjin Kim

Jaehoon Lee

Jongwoo Lee

Sangdon Jung

Suseob Ahn

Hyungi Seok

An electronic device includes: a first equalizing circuit configured to receive a data signal and output a first equalizing signal based on the data signal; a pulse generator configured to generate a first pulse signal and a second pulse signal in response to a rising edge and a falling edge of the data signal, respectively; a second equalizing circuit configured to output a second equalizing signal based on the first pulse signal and the second pulse signal that have been inverted; and an output terminal configured to output an output signal in which the first equalizing signal and the second equalizing signal have been summed.

Electronic device including equalizing circuit and operating method of the electronic device

A phase-locked loop (PLL) circuit may include a voltage-controlled oscillator, a sub-sampling PLL circuit, and a fractional frequency division control circuit. The fractional frequency division control circuit may include a voltage-controlled delay line that routes a feedback signal to generate delay information, a replica voltage-controlled delay line to which the delay information is applied and configured to route a reference clock signal to generate a plurality of delay reference clock signals each delayed by up to a different respective delay time, and a digital-to-time converter (DTC) configured to generate the selection reference clock signal from the plurality of delay reference clock signals and output the selection reference clock signal to the sub-sampling PLL circuit.

Phase-locked loop circuit and clock generator including the same

The ABB blocksandare configured to process the I/Q signals corresponding to the first or the second HB independently or the I/Q signals corresponding to the LB in cooperation by two. In detail, the first ABB I blockand the first ABB Q blockoperate independently in the 3G/4G mode but they are configured to process the I signal (or Q signal) of the LB in the 2G mode. Likewise, the second ABB Q blockand the second ABB I blockoperate independently in the 3G/4G mode but they are configured to process the Q signal (or I signal) of the LB in the 2G mode. The first ABB I/Q blocksandand the second ABB I/Q blocksandare arranged symmetrically to processing the I/Q signals cooperatively in the 2G mode. In detail, the second ABB Q blockis arranged close to the first ABB Q blocksuch that the capacitor regions included in the first ABB I/Q blocksandare connected to each other and the capacitor regions included in the second ABB I/Q blocksandare connected to each other.

Analog baseband filtering apparatus of multimode multiband wireless transceiver and control method thereof

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Yongin-si, South Korea

Byungki Han