Samsung Electronics Co., Ltd.

Byungju Kang

Sungho Park

Yubo Qian

Seonah Nam

Hyelim Kim

Byungsung Kim

Kwanyoung Chun

Chulhong Park

Moon Gi Cho

Panjae Park

Jiwook Kwon

Yoonjeong Kim

Janie Hyojin Kim

Suhyeong Choi

A semiconductor device includes: a semiconductor substrate having power arrangement regions; a first interconnection structure disposed on the semiconductor substrate and including first interconnection patterns and power lines; a second interconnection structure disposed on the semiconductor substrate and including second interconnection patterns; and through-electrodes passing through each of the power arrangement regions and contacting the power lines, wherein the first interconnection patterns include first interconnection lines, wherein the power lines are disposed on a same height level as a first interconnection line, among the first interconnection lines, and are parallel to each other, wherein the power arrangement regions are parallel to each other, and wherein intersection regions, in which the power arrangement regions and the power lines intersect, include a plurality of first active intersection regions, one dummy intersection region, and a plurality of second active intersection regions, sequentially arranged.

Semiconductor devices

A semiconductor device includes first and second external dummy areas, and a circuit area between the first and second external dummy areas. The circuit area includes circuit active regions and circuit gate lines. Each external dummy area includes an external dummy active region and external dummy gate lines overlapping the external dummy active region and spaced apart from the circuit gate lines. The external dummy active region has a linear shape extending in a first horizontal direction or a shape including active portions isolated from direct contact with each other and extending sequentially in the first horizontal direction. The circuit active regions are between the first and second external dummy active regions and include a first plurality of circuit active regions extending sequentially in the first horizontal direction and a second plurality of circuit active regions extending sequentially in a second horizontal direction perpendicular to the first horizontal direction.

Semiconductor devices with circuit active elements and dummy active elements

Semiconductor devices with circuit and external dummy areas

An integrated circuit chip including a substrate including first and second element regions; a first channel active region extending in a first direction; a second channel active region; gate lines extending in a second direction and intersecting the first and second channel active regions; a diffusion break extending in the second direction; source/drain regions at opposite sides of the gate lines and on the first and second channel active regions; a first power line electrically connected to the source/drain regions; and a second power line electrically connected to the source/drain regions and having a lower voltage level than the first power line, wherein the diffusion break includes a first region including an insulator and overlapping the first element region, and a second region including a same material as the gate lines and overlapping the second element region, wherein the second region is electrically connected to the second power line.

Integrated circuit chip including standard cell

A semiconductor device and a fabricating method thereof are provided. The method includes sequentially forming an interlayer insulating layer and a hard mask layer on a substrate with first and second regions, performing a first patterning process on the hard mask layer to form first openings in the first and second regions, performing a second patterning process on the hard mask layer to form second openings in the first and second regions, and performing a third patterning process on the hard mask layer to selectively form at least one third opening in only the second region. The third patterning process includes forming a first photoresist pattern with openings on the hard mask layer, and the opening of the first photoresist pattern on the first region is overlapped with the second opening on the first region, when viewed in a plan view.

Semiconductor device and method of fabricating the same

Growing community of inventors

Seoul, South Korea

Byungju Kang