Lg Display Co., Ltd.

Byungil Kim

Changho An

Seokhwan Choi

A display device comprises a display panel and a timing controller. The timing controller supplies gate timing signals to a gate driver as a sequence of clock pulses that sequentially select different ones of the display lines for receiving the data signals during the vertical active periods and for receiving a sensing signal during the vertical blanking intervals. The clock pulses have a first timing during the vertical active periods and the clock pulses have a second timing during the vertical blanking intervals in which the second timing is different than the first timing.

External compensation for a display device using varying gate pulse timing

A driving circuit for real-time external compensation and an electroluminescent display including the same are disclosed. The driving circuit includes a timing controller generating a gate shift clock group, a gate start pulse, and first and second selection signals and a gate driver generating a gate signal based on the control of the timing controller and supplying the gate signal to a display panel. The gate driver includes a plurality of stages which shifts the gate start pulse in accordance with the gate shift clock group to generate an output signal and supplies the output signal to a first output node, a first output control switch connected between a second output node connected to a gate line of the display panel and the first output node, and a second output control switch connected between the second output node and an input terminal of a gate low voltage.

Driving circuit for real-time external compensation and electroluminescent display including the same

A display device comprises a display panel and a timing controller. Electrical characteristics of sensing target display lines of the display panel are sensed during the sensing periods of vertical active periods of sensing drive frames. Data lines are driven with data signals without sensing the display lines during the vertical active periods of normal drive frames and during display periods of the vertical active periods of the sensing drive frames. A timing controller supplies timing signals to a gate driver as a plurality of clock pulses to control timing of the gate driver providing gate pulses to the gate lines. The clock pulses have a first timing during the vertical active periods of the sensing drive frames and the clock pulses have a second timing during the vertical active periods of the normal drive frames in which the second timing is different than the first timing.

External compensation for a display device and method of driving the same

A driver integrated circuit for external compensation and a display device including the same are disclosed. The driver integrated circuit includes a sensing unit including a plurality of sensing switches, that is connected to a plurality of pixels through a sensing channel and operates differently depending on a current sensing mode and a voltage sensing mode, the sensing unit configured to sense electrical characteristics of the pixels input from the sensing channel, a sample and hold unit configured to sample analog sensing data corresponding to the electrical characteristics of the pixels, and an analog-to-digital converter (ADC) configured to convert the analog sensing data sampled by the sample and hold unit into digital sensing data.

Driver integrated circuit for external compensation and display device including the same

A driver integrated circuit and a display device including the same are disclosed. The driver integrated circuit includes a data voltage generator that includes a digital-to-analog converter converting a digital signal into an analog signal, generates an analog data voltage in a display drive operation, and applies the analog data voltage to pixels of a display panel, a sensor that is connected to a sensing channel connected to the pixels of the display panel, shares the digital-to-analog converter with the data voltage generator, converts an analog sensing voltage indicating electrical characteristics of the pixels input from the sensing channel into digital sensing data in a sensing drive operation, and outputs the digital sensing data, and switching elements selectively operating in the display drive operation and the sensing drive operation.

Driver integrated circuit and display device including the same

A driver integrated circuit, a display device including the driver integrated circuit, and a data correction method of the display device are disclosed. The driver integrated circuit includes a voltage generator generating a sensing data voltage, a calibration unit that decodes N-bit calibration data input from the voltage generator and generates at least one calibration voltage, where N is a positive integer, a sensor that samples a signal output from a pixel corresponding to the sensing data voltage in a sensing mode for sensing electrical characteristics of the pixel and samples the calibration voltage in a calibration mode for sensing output characteristics of an analog-to-digital converter, and the analog-to-digital converter converting an analog signal sampled by the sensor into a digital signal.

Driver integrated circuit for external compensation, display device including the same, and data correction method of display device

Provided are a gate driving circuit and a display device including the same. The gate driving circuit according to an embodiment includes a shift register including a plurality of stages. An nth stage of the stages includes a latch control circuit including a first NMOS transistor connected to a QB node, a second NMOS transistor connected to a Q node, and a third NMOS transistor having a gate electrode to which a first clock is input and connected to the first and second NMOS transistors, where n is a positive integer. A latch is connected between the Q and QB nodes. A transmission gate is connected to the Q and QB nodes. In the gate driving circuit, output signals of a previous stage and a following stage are controlled so as to be synchronized with the first clock to suppress a glitch.

Gate driving circuit and display device including the same

Provided are a GIP driving circuit and a display device using the same. The GIP driving circuit includes: a plurality of stages which sequentially receives a phase-delayed clock and sequentially generates an output. An nth stage (n is a positive integer) includes: a first switch Treceiving a carry signal from an n&#x2212;1th stage and controlling a QB node to a low voltage and a Q node to a high voltage when the carry signal has a high voltage; a second switch Treceiving a carry signal from an n+1th stage and controlling the QB and Q nodes high and low voltages, respectively, when the carry signal has a high voltage; a plurality of inverters connected between nodes Q and QB and constituting a latch; and a buffer outputting a clock as an output voltage when a voltage of the Q node is a high voltage and output.

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Gimpo-si, South Korea

Byungil Kim