Texas Instruments Corporation

The University of Texas System

Byungchul Jang

Timothy Bryan Merkin

Erick Omar Torres

Adam Lee Shook

Nghia Trong Tang

Arjang Hassibi

Harish Venkataraman

Arun Manickam

Hassan Pooya Forghani-Zadeh

Roland Karl Son

Pankaj Pandey

An apparatus includes a transistor coupled between an input pin and an output pin and an overvoltage detection circuit configured to receive a serial interface signal from the input pin and generate an enable signal in response to a voltage of the serial interface signal exceeding a voltage threshold. The apparatus also includes a first circuit configured to apply a clamping voltage to a gate of the transistor based on the enable signal to regulate a voltage provided at the output pin.

Suppressing overvoltage transients in a serial interface

Frequency lock loop (FLL) circuits, low voltage dropout regulator circuits, and related methods are disclosed. An example gate driver integrated circuit includes a first die including a FLL circuit to generate a first clock signal having a first phase and a first frequency, a second clock signal having the first frequency and a second phase different from the first phase, and control a plurality of switching networks to increase the first frequency to a second frequency, and generate a feedback voltage based on the second frequency, and a second die coupled to the first die, the second die including a low dropout (LDO) circuit and a driver, the driver configured to control a transistor based on the first frequency, the second die configured to be coupled to the transistor, the LDO circuit to generate a pass-gate voltage based on an output current of the LDO circuit satisfying a current threshold.

Frequency lock loop circuits, low voltage dropout regulator circuits, and related methods

An integrated circuit (IC) comprises an output and a voltage regulator. The voltage regulator comprises an amplifier having a first input coupled to a reference voltage source and a second input coupled to the output, a first resistor coupled to the output and coupled to a ground terminal, a metal oxide semiconductor field effect transistor (MOSFET) having a gate coupled to an output of the amplifier and a drain coupled to the output, and a second resistor coupled to a source of the MOSFET and coupled to the ground terminal.

Voltage regulator in USB power delivery integrated circuit

USB controllers, systems and methods are presented to conserve power in a USB controller, in which a transmitter transmits data to a line of a connected USB cable according to a transmit data signal, and a pull down circuit selectively sinks current from a supply node of the transmitter when the transmit data signal is in a first state, refrains from sinking the first current from the supply node when the transmit data signal is in a different second state.

Circuit and method for interfacing universal serial bus

A circuit for minimizing variation over process, voltage and temperature for edge rate over and propagation delay. The circuit includes at least two first buffers for decoupling large nonlinear parasitic capacitors of the main drivers, at least two second buffers for level shifting to the at least two first buffers, at least two voltage sources for initializing the stage of at least one of the first or the second buffer, and a current source generator coupled to the voltage source of the second buffers.

Method, apparatus and system for an edge rate controlled output buffer

A Charge Pump Buck Converter (CPBC) includes a BC including an inductor and a CP coupled in parallel. Control logic is coupled to a switch driver coupled to a power switch(es). Control circuitry includes a voltage sensor sensing Vout and a voltage level generator for generating a first voltage level coupled to the CP stage and a second voltage level coupled to a duty cycle/rate generator block providing an input to an under voltage (UV) monitor coupled between OUT and the control logic. The control circuitry disables the CP when Vout&#x3e;a first Vout level and controls the BC to regulate to a second Vout level&#x3e;the first Vout level. During handoff between CP and BC during power up if Vout drops below a UV threshold, the UV monitor block modifies an input applied to the control logic for increasing charging supplied to the inductor.

Droop reduction circuit for charge pump buck converter

A switch-mode DC-DC voltage converter including a boost stage in the form of a charge pump and a buck stage. Control circuitry is provided that enables the operation of the buck stage while the charge pump stage is also enabled, followed by disabling of the charge pump stage as the input voltage and output voltage increase. The buck converter stage is constructed so that it regulates the output voltage at a voltage above that which disables the charge pump stage. Conduction losses in the main current path, due to the necessity of a power FET or other switching device, are avoided.

Low-loss step-up and step-down voltage converter

A biosensor system incorporating CMOS integrated circuits. In one type of biosensor system, the biosensor system includes a silicon substrate. The biosensor system further includes active devices fabricated on the silicon substrate. Additionally, the biosensor system includes a plurality of metal layers stacked on top of the active devices. Furthermore, the biosensor system includes a passivation layer covering a top metal layer, where the passivation layer includes an opening configured to expose the top metal layer, where the opening is used as a sensing electrode. Additionally, the biosensor system includes a plurality of probes attached to the sensing electrode.

Incorporating CMOS integrated circuits in the design of affinity-based biosensor systems

Traditionally, charge pumps, which used flying capacitors, were limited to a maximum divide ratio of N+1 (where N is the number of flying capacitors). Here, however, a charge pump has been provided that allows for a dramatically increased divide ratio. Specifically, several switched capacitor circuits (which are controlled by a driver) allow for flying capacitors to be arranged to provide a maximum divide ratio of 3&#xb7;2&#x2212;1.

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Allen, TX, United States of America

Byungchul Jang