Samsung Electronics Co., Ltd.

Byung Tak Lee

Sang Woo Kim

Jong Ho Roh

Kyoung Man Kim

Yun Ju Kwon

Joon-Woo Cho

Yoo Seok Shon

Provided are a semiconductor device and a semiconductor system. A semiconductor device includes a hardware auto clock gating (HWACG) logic configured to provide clock gating of an intellectual property (IP) block; and a memory power controller configured to perform power gating of a memory electrically connected with the IP block, based on the HWACG logic providing the clock gating for the IP block. The HWACG logic includes a first clock source configured to provide a first clock signal; a second clock source configured to receive the first clock signal provided by the first clock source, and provide a second clock signal to the IP block; a first clock control circuit configured to control the first clock source; and a second clock control circuit configured to transmit a clock request to the first clock control circuit, and control the second clock source, based on an operation state of the IP block.

Semiconductor device and semiconductor system

A system on chip (SoC) for transmitting data packets to a display driver integrated circuit (IC) controlling a plurality of displays is provided. The SoC includes a first register, and a central processing unit (CPU) configured to set first values in the first register to adjust a frame rate of each of the displays. A tearing effect (TE) signal detection circuit is configured to detect a TE signal output from the display driver IC. A data transmission circuit is configured to generate a plurality of frame rate adjustment signals using the detected TE signal and the first values and to control transmission timings of the data packets transmitted to the displays using the frame rate adjustment signals.

Host and multi-display system including the same

Growing community of inventors

Jeju-si, South Korea

Byung Tak Lee