Samsung Electronics Co., Ltd.

Sungkyunkwan University

Byung-Sung Kim

Chul-hong Park

Jung-Ho Do

Byoung-lyong Choi

Dong-mok Whang

Vincent Chun Fai Lau

Eun-kyung Lee

Sanghoon Lee

Ju-Youn Kim

Hwa-Sung Rhee

Yoon-Hae Kim

Eun-Kyung Lee

Won-Jae Joo

Bong-Seok Suh

Jae-hyun Lee

Jong-shik Yoon

Yubo Qian

Gyuyeol Kim

Haewang Lee

Jae-Woong Choi

Jong-woon Lee

Sang-Min Yoo

Hyung-Joo Na

Sung-Moon Lee

Joo-Ho Jung

Yun-hyok Choi

Eui-Chul Hwang

Cheol-heui Park

Sungjung Kim

Disclosed is a fan-out buffer which includes a first channel that includes a first delay circuit adjusting a first delay time of a calibration test signal depending on a first delay control signal, a second channel that includes a second delay circuit adjusting a second delay time of the calibration test signal depending on a second delay control signal, a first edge-to-pulse converter that detects a first edge included in a first time domain reflectometry (TDR) waveform of an output terminal of the first channel and generates a first start pulse signal including a first pulse, a second edge-to-pulse converter that generates a second start pulse signal including a second pulse, a stop pulse signal generator that generates a stop pulse signal including a first stop pulse, and a first delay control signal generator that calculates a phase difference generates the first delay control signal.

Fan-out buffer with skew control function, operating method thereof, and probe card including the same

A semiconductor device may include active fins each of which extends in a first direction on a substrate, the active fins being spaced apart from each other in a second direction different from the first direction, a conductive structure extending in the second direction on the substrate, the conductive structure contacting the active fins, a first diffusion break pattern between the substrate and the conductive structure, the first diffusion break pattern dividing a first active fin of the active fins into a plurality of pieces aligned in the first direction, and a second diffusion break pattern adjacent to the conductive structure on the substrate, the second diffusion break pattern having an upper surface higher than a lower surface of the conductive structure, and dividing a second active fin of the active fins into a plurality of pieces aligned in the first direction.

Semiconductor devices

A semiconductor device includes a substrate; a plurality of conductive areas formed on the substrate at a first vertical level; a first wiring layer formed on the substrate at a second vertical level which is higher than the first vertical level, the first wiring layer including first lines that extend in a first direction, one first line of the first lines connected to a first conductive area selected from the plurality of conductive areas through a via contact; a second wiring layer formed on the substrate at a third vertical level which is higher than the second vertical level, the second wiring layer including second lines that extend in a second direction that crosses the first direction, one second line of the second lines connected to a second conductive area selected from the plurality of conductive areas; and a deep via contact spaced apart from lines of the first wiring layer in a horizontal direction and extending from the second conductive area to the one second line.

Logic cell including deep via contact and wiring layers located at different levels

Disclosed are a semiconductor device and a method of manufacturing the same. The semiconductor device includes first and second logic cells adjacent to each other in a first direction on a substrate, a gate electrode extending in the first direction in each of the first and second logic cells, a power line extending in a second direction at a boundary between the first and second logic cells, and a connection structure electrically connecting the power line to an active pattern of the first logic cell and to an active pattern of the second logic cell. The connection structure lies below the power line and extends from the first logic cell to the second logic cell. A top surface of the connection structure is at a higher level than that of a top surface of the gate electrode.

Semiconductor device having shared power line connections and method of manufacturing the same

Logic cell including single layer via contact and deep via contact

Provided are method of fabricating semiconductor device and computing system for implementing the method. The method of fabricating a semiconductor device includes forming a target layer, forming a first mask on the target layer to expose a first region, subsequently forming a second mask on the target layer to expose a second region separated from the first region in a first direction, subsequently forming a third mask in the exposed first region to divide the first region into a first sub region and a second sub region separated from each other in a second direction intersecting the first direction, and etching the target layer using the first through third masks such that the first and second sub regions and the second region are defined in the target layer.

Method of fabricating semiconductor device and computing system for implementing the method

Logic cell, semiconductor device including logic cell, and method of manufacturing the logic cell and semiconductor device

According to example embodiments, a wire structure includes a first wire that includes a first wire core and a first carbon shell surrounding the first wire core, and a second wire that extends in a longitudinal direction from the first wire. The first wire core has a wire shape. The first carbon shell contains carbon.

Wire structure and semiconductor device having the same, and method of manufacturing the wire structure

A method of synthesizing a nanowire. The method includes disposing a first oxide layer including germanium (Ge) on a substrate, forming a second oxide layer including a nucleus by annealing the first oxide layer, and growing a nanowire including Ge from the nucleus by a chemical vapor deposition ('CVD') method.

Method of synthesizing nanowires

A composite structure and a method of manufacturing the composite structure. The composite structure includes a graphene sheet; and a nanostructure oriented through the graphene sheet and having a substantially one-dimensional shape.

Composite structure and method of manufacturing the same

Growing community of inventors

Suwon-si, South Korea

Byung-Sung Kim