Hynix Semiconductor Inc.

Skhynix Inc.

Byung Soo Park

Sung Jae Chung

Sang Hyun Oh

Sun Mi Park

Seo Hyun Lee

Byung Jin Ahn

Sang Tae Ahn

Yung Jun Kim

Won Hyo Cha

Jung Ryul Ahn

Jong Ho Jung

Eun Mi Kim

Sang Hyuk Nam

Hee Sik Park

Joo Won Hwang

Hack Seob Shin

Hae Jung Lee

Kyeong Bock Lee

Ga Hee Lee

Sung Yoon Cho

A semiconductor device includes stack structures each including a first conductive layer, a substrate disposed under the stack structures, first impurity regions disposed in the substrate, and at least one trench passing through the stack structures and disposed above the first impurity regions.

Semiconductor device and manufacturing method of the semiconductor device

A non-volatile memory device according to an aspect of the present disclosure includes a substrate, a plurality of word lines stacked over the substrate and having a stepwise pattern, wherein the plurality of word lines each have a pad region, and a plurality of contact plugs coupled to the respective pad regions of the word lines, wherein a width of a pad region of a first one of the plurality of word lines is greater than a width of a pad region of a second word line lower than the first word line.

3-D structured non-volatile memory device and method of manufacturing the same

A semiconductor device may include a substrate, conductive patterns stacked to be spaced apart from each other on the substrate, contact plugs coming in contact with the respective conductive patterns, and first and second slit insulating layers of a first group penetrating the conductive patterns. The substrate may include a cell area and a contact area extending along a first direction from the cell area. The conductive patterns may be form a step structure. The first slit insulating layers of the first group may be opposite to each other in a second direction with any one of the contact plugs, interposed therebetween. The second slit insulating layers of the first group, which extend along the first direction in the contact area, may be opposite to each other in the second direction with the first slit insulating layers of the first group and the contact plugs, interposed therebetween.

Semiconductor device and manufacturing method thereof

A three dimensional (3-D) non-volatile memory device includes a pipe gate including a first pipe gate, a second pipe gate formed on the first pipe gate, and a first interlayer insulating layer interposed between the first pipe gate and the second pipe gate, word lines alternately stacked with second interlayer insulating layers on the pipe gate, a pipe channel buried within the pipe gate, and memory cell channels coupled to the pipe channel and arranged to pass through the word lines and the second interlayer insulating layers.

3-D non-volatile memory device and method of manufacturing the same

A method of manufacturing a flash memory device. According to the invention, a floating gate can be formed and a distance between cells can be secured sufficiently by using one conductive layer without using a SA-STI process that cannot be applied to the manufacturing process of highly integrated semiconductor devices. It is therefore possible to minimize interference between neighboring cells.

Method of manufacturing flash memory device with conductive spacers

A method of forming a semiconductor device includes etching a semiconductor substrate to form a first trench having a first width and a first depth; etching the semiconductor substrate to form a second trench having a second width and a second depth, the second trench overlapping the first trench, the second width being greater than the first width, the second depth being less than the first depth, whereby a trench having a dual structure is formed; and forming a first isolation structure within the trench having the dual structure. An embodiment of the present invention relates to a method of forming an isolation structure of a semiconductor device.

Method of forming isolation structure of semiconductor device

The present disclosure relates to methods of forming a flash memory device. A plurality of cells, a plurality of select transistors, and a transistor are formed over a semiconductor substrate including a cell region and a peripheral region. An insulating layer is formed on the entire surface. Metal contact holes are etched and filled with a metal contact layer. Drain contact holes are also etched and filled with a drain contact layer. The order of the metal contact layer formation and drain contact layer formation can be reversed. A single chemical mechanical polishing step is performed to remove the top portions of the metal and drain contact layers, thereby exposing the top surface of the interlayer insulating layer and simultaneously forming both the metal and drain contacts.

Methods of forming flash memory device

A method of forming a resistor of a flash memory device includes etching an isolation structure provided on a semiconductor substrate to form a first trench. A polysilicon structure is formed within the first trench of the isolation structure. A dielectric layer is formed on the polysilicon structure. A polysilicon layer is formed over the dielectric layer. The polysilicon layer is etched to define second and third trenches in the polysilicion layer. The second and third trenches separates the polysilicon layer into first, second, and third sections, where the first and third section contact the polysilicon structure, and the second section is separated from the first and third sections. An insulating film is formed over the etched polysilicion layer, the insulating film filling the second and third trenches. the first section of the polysilicon layer, the polysilicon structure, and the third section of the polysilicon layer define a resistor.

Method of forming resistor of flash memory device

A flash memory device comprises a first group of dummy memory cells disposed between source selection transistors, which are coupled to a source selection line, and memory cells coupled to a first wordline. The flash memory device further comprises a second group of dummy memory cells disposed between drain selection transistors, which are coupled to a drain selection line, and memory cells coupled to the last wordline. The flash memory device is configured to prevent program disturbance in deselected cell strings and degradation of programming/erasing speeds in a selected cell string.

Flash memory device

The present invention relates to a flash memory cell and method of manufacturing the same, and programming/erasing/reading method in the flash memory cell. According to the present invention, a source region and a drain region are first formed and a tunnel oxide film is then formed. Therefore, it is possible to prevent damage of the tunnel oxide film due to an ion implantation process. Further, independent two channel regions are formed below the floating gate. Thus, it is possible to store data of two or more bits at a single cell. In addition, the tunnel oxide film, the floating gate and the dielectric film having an ONO structure are formed at a given regions. It is thus possible to reduce the steps of a process and improve an electrical characteristic and integration level of a device.

Flash memory cell and method of manufacturing the same, and programming/erasing/reading method in the flash memory cell

A method of forming a select line in a NAND type flash memory device is disclosed. In the select line having a stack structure of the floating gate, the dielectric film and the control gate, the control gate is patterned so that a first projection is formed at the edge of the control gate, and the floating gate is formed by means of the self-aligned etch process. At this time, the floating gate is patterned so that a second projection the one end of which overlaps the first projection is formed at the edge of the floating gate. Next, the first and second projections are electrically connected using the contact plugs and the metal line, whereby a voltage is simultaneously applied to the control gate of a low resistance and the floating gate of a high resistance. Therefore, the present invention can minimize generation of voltage drop to improve electrical characteristics, and obviate a process of removing the dielectric film for electrically connecting the floating gate and the control gate to simplify the process steps.

Growing community of inventors

Ichon-shi, South Korea

Byung Soo Park