Samsung Electronics Co., Ltd.

Byung-seo Kim

Hye-Jin Kim

Beom-jun Jin

Sung-Dong Kim

Du-Eung Kim

Beak-Hyung Cho

Eun-jung Yun

Sun-Pil Youn

Sung-min Kim

Yoon-jong Song

Sa-Yoon Kang

Kyung-Chang Ryoo

Min-Young Son

Jong-Soo Seo

Kyoung-sei Choi

Si-hoon Lee

Ye-chung Chung

Kyong-Soon Cho

Young-sang Cho

Sang-Gui Jo

Dae-woo Son

Sang-Heui Lee

Young-jae Joo

Jeong-kyu Ha

Mu-Seob Shin

Ho Young Lee

Hwa-Sung Rhee

Ji-Hye Yi

Young-hee Song

Tae-Sung Yoon

Myung-sun Kim

Jong-bong Park

Hion-suck Baik

Sunpil Youn

Jung-Yun Won

Min-Keun Kwak

Sun-il Youn

A NAND based non-volatile memory device can include a plurality of memory cells vertically arranged as a NAND string and a plurality of word line plates each electrically connected to a respective gate of the memory cells in the NAND string. A plurality of word line contacts can each be electrically connected to a respective word line plate, where the plurality of word line contacts are aligned to a bit line direction in the device.

Methods of forming non-volatile memory devices including vertical NAND strings

A plurality of semiconductor chips may be stacked on the substrate, and each of them may include at least one electrode pad. At least one of the plurality of semiconductor chips may include at least one redistribution pad configured to electrically connect with the at least one electrode pad.

Semiconductor packages and electronic systems including the same

Non-volatile memory devices including vertical NAND strings and methods of forming the same

Provided are semiconductor packages and electronic systems including the same. A substrate is provided. A plurality of semiconductor chips may be stacked the substrate, and each of them may include at least one electrode pad. At least one of the plurality of semiconductor chips may include at least one redistribution pad configured to electrically connect with the at least one electrode pad.

Disclosed is a chip-on-film (COF) type semiconductor package and a device using the same. The COF type semiconductor package may include an insulation substrate including a top surface and bottom surface, a semiconductor device on the top surface of the insulation substrate, a heat dissipating component on the bottom surface of the insulation substrate, and at least one space between the bottom surface of the insulation substrate and a top surface of the heat dissipating component.

Tape for heat dissipating member, chip on film type semiconductor package including heat dissipating member, and electronic apparatus including the same

In a semiconductor memory device and method, resistive-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices comprising a resistive-change memory. Each resistive-change memory cell includes a plurality of control transistors formed on different layers, and a variable resistance device formed of a resistive-change memory. In one example, the number of the control transistors is two. The semiconductor memory device includes a global bit line; a plurality of local bit lines connected to or disconnected from the global bit line via local bit line selection circuits which correspond to the local bit lines, respectively; and a plurality of resistive-change memory cell groups storing data while being connected to the local bit lines, respectively. Each of the resistive-change memory cells of each of the resistive-change memory cell groups comprises a plurality of control transistors formed on different layers, and a variable resistance device formed of a resistive-change memory. In addition, the semiconductor memory device has a hierarchical bit line structure that uses a global bit line and local bit lines. Accordingly, it is possible to increase both the integration density of the semiconductor memory device and the amount of current flowing through each of the resistive-change memory cells.

Semiconductor memory device with stacked memory cell and method of manufacturing the stacked memory cell

A method of fabricating a phase change memory includes forming a lower electrode on a semiconductor substrate, forming a phase change pattern, an upper electrode, and a hard mask pattern sequentially on the lower electrode, a width of a bottom surface of the hard mask pattern being greater than a width of a top surface of the hard mask pattern, the bottom surface of the hard mask pattern facing the upper electrode and being opposite the top surface of the hard mask pattern, and forming a capping layer to cover the top surface of the hard mask pattern and sidewalls of the hard mask pattern, phase change pattern, and upper electrode.

Phase change memory

Provided are a semiconductor package, a method of forming the semiconductor package, and a printed circuit board (PCB). The semiconductor package includes: a PCB including at least two parts divided by an isolation region; a semiconductor chip mounted on the PCB; and a molding layer disposed in the isolation region. The method includes: preparing a PCB, the PCB including a plurality of chip regions and a scribe region; forming isolation regions dividing each of the chip regions into two parts, the isolation regions including inner isolation regions and outer isolation regions, the inner isolation regions being provided in the chip regions, the outer isolation regions being provided at both ends of the inner isolation regions so as to extend toward the scribe region; mounting semiconductor chips on the chip regions; and cutting the PCB along the scribe region to divide the chip regions into at least two parts.

Semiconductor package and method of forming the same, and printed circuit board

In one aspect, a method of fabricating a semiconductor device is provided. The method includes forming at least one capping layer over epitaxial source/drain regions of a PMOS device, forming a stress memorization (SM) layer over the PMOS device including the at least one capping layer and over an adjacent NMOS device, and treating the SM layer formed over the NMOS and PMOS devices to induce tensile stress in a channel region of the NMOS device.

Methods of fabrication of channel-stressed semiconductor devices

Phase change memory and method of fabricating the same

Growing community of inventors

Suwon-si, South Korea

Byung-seo Kim