Samsung Electronics Co., Ltd.

Byung-Se So

Jeong-Hyeon Cho

Seung-Jin Seo

Jung-Joon Lee

Seung-Man Shin

Dong-Ho Lee

You-Keun Han

Jae-jun Lee

Hyun-Soon Jang

Young-Man Ahn

Jae-Jun Lee

Young-Jun Park

Do-Hyung Kim

Jung-bae Lee

Hoe-Ju Chung

Jong-Hoon Kim

Young Nam Yun

Kwang-Soo Park

Sung-bum Cho

Woo-seop Kim

Seok-Il Kim

Kwang-Seop Kim

Jung-Kuk Lee

Hui-chong Shin

Hyun-Chul Kang

Chil-Nam Yoon

Jun-young Park

Ho-Suk Lee

Sung-Joo Park

Chang-Woo Koo

Myun-Joo Park

Sung-Je Hong

Jin-Kyu Chang

Il-Sung Yu

Example embodiments relate to a method and system of testing a memory module having the process of receiving single ended input signals via differential input terminals through which differential pairs of packet signals may be received from a testing equipment, wherein a number of terminals of the testing equipment may be different from a number of terminals of the memory module, and testing memory chips of the memory module based on the single ended input signals.

Method of testing a memory module and hub of the memory module

A semiconductor memory device capable of determining an operation mode by using states of data pins, and an operation mode determining method for the same are disclosed. The semiconductor memory device includes at least one MRS input pad, at least one data input pad, and an operation mode determining circuit. The operation mode determining circuit generates an operation mode determining signal, when an MRS command input through the MRS input pad corresponds to a predetermined MRS command and data signals input through the data input pad or pads include a predetermined combination. Accordingly, the efficiency in the manufacturing and producing processes may be improved by determining the operation mode of the semiconductor memory device in a module assembly process.

Determining operation mode for semiconductor memory device

Multi-chip package includes first through Nth semiconductor chips, each of which includes an input/output pad, an input/output driver coupled to the input/output pad, and an internal circuit. Each of the first through Nth semiconductor chips includes an internal pad for coupling the internal input/output driver and the internal circuit. The internal pads of the first through Nth semiconductor chips are coupled to each other such as via a common pad installed at a substrate. The input/output pad of the first semiconductor chip directly receives an input/output signal transmitted via a corresponding pin of the multi-chip package. The second through Nth semiconductor chips indirectly receive the input/output signal via the internal pads coupled to each other. The multi-chip package can improve signal compatibility by maintaining a parasitic load of a pin to at least the level of a single chip, when a signal is transmitted to the pin at high speed. Also, when a signal that is not necessarily transmitted at high speed is applied to a pin, semiconductor chips can be packaged according to the preexisting methods.

Multi-chip package for reducing parasitic load of pin

A multi-chip package includes first through Nth semiconductor chips, each of which includes an input/output pad, an input/output driver coupled to the input/output pad, and an internal circuit. Each of the first through Nth semiconductor chips includes an internal pad for coupling the internal input/output driver and the internal circuit. The input/output pad of the first semiconductor chip directly receives an input/output signal via a corresponding pin of the multi-chip package. The second through Nth semiconductor chips indirectly receive the input/output signal via the internal pads coupled to each other. The multi-chip package can improve signal compatibility by maintaining a parasitic load of a pin to at least the level of a single chip, when a signal is transmitted to the pin at high speed.

Pairs of registers with reduced pins are disposed to overlap on front and back surfaces of a memory module. An input signal INS is transferred through the registers in series in a daisy chain fashion to avoid divergence of the input signal INS for preserved signal integrity. Each register buffers the input signal INS to memory banks disposed closely to sides of the register for reduced wiring area.

Memory module with registers

A test apparatus capable of detecting input/output (I/O) circuit characteristics of a semiconductor device by analyzing an eye mask generated in the test apparatus and the waveform of a test signal output from the I/O circuit of the semiconductor device. The test apparatus includes an eye mask generator that generates an eye mask in synchronization with one or more clock signals of opposite phase to each other, an error detector that receives the eye mask from the eye mask generator and compares the test signal with the eye mask to determine whether an error occurs in the semiconductor device, and an error signal output unit that receives an error detection signal from the error detector and generates an error signal in response to the error detection signal. In particular, the eye mask generator includes a sine wave generator that generates one or more sine waves of opposite phase to each other in synchronization with one or more clock signals, and a limiter circuit that receives the sine waves and generates the eye mask by adjusting the amplitudes of the sine waves.

Apparatus and method for testing circuit characteristics by using eye mask

Embodiments are described in which a stacked arrangement of integrated circuit packages comprises a dummy substrate comprising an embedded discrete or distributed capacitor connected to first and/or second power voltages, or an embedded termination register connected to one or more clock, control, address, and/or data signals(s).

Memory module with stacked semiconductor devices

A memory module, a memory unit, and a hub with a non-periodic clock and methods for using the same. An example memory module may include a phased locked loop, receiving an external, periodic clock and generating one or more internal periodic clocks and a plurality of memory units, receiving one of the internal periodic clocks or a non-periodic clock from an external source.

Memory module, memory unit, and hub with non-periodic clock and methods of using the same

A memory module test system including at least one memory module. The at least one memory module includes a first hub and a plurality of semiconductor memory devices. The system includes a tester for testing the at least one memory module. A second hub is located between the first hub and the tester. The second hub is for converting a memory command and memory data output from the tester into packet data and transmits the packet data to the first hub. The second hub converts the packet data output from the first hub into memory data and transmits the memory data to the tester.

Memory module test system for memory module including hub

A data transmission system and method characterized by the use of multiple differential output amplifiers to transmits differential data signals that vary in accordance with control signals derived from a reference data output strobe signal, and multiple differential amplifiers to receive the differential data signals and detect such variations to generate a data input strobe signal corresponding to the data output strobe signal.

Data transmission system and method

A method of testing a memory module comprising converting a hub of the memory module into a transparent mode, providing first data corresponding to a first address to the hub of the memory module, providing the first data of the hub of the memory module to a first address of a memory, providing first expected data to the hub of the memory module, outputting second data stored at the first address of the memory to the hub of the memory module, and comparing the second data with the first expected data.

A buffered memory module includes a buffer circuit mounted and a plurality of memory devices mounted on the first surface of the board, the memory devices being electrically connected to the buffer circuit. The memory module also includes a plurality of test pads located on a second surface of the board and electrically connected to the buffer circuit.

Buffered memory module and method for testing same

Embodiments of the invention include a stacked board-on-chip (BOC) package having a mirroring structure and a dual inline memory module (DIMM) on which the stacked BOC package is mounted. A bottom surface of a first semiconductor chip faces a bottom surface of a second semiconductor chip. An interposer electrically connects first and second packages, respectively comprising the first and second semiconductor chips, to each other. The DIMM is obtained by electrically connecting BOC packages to each other on upper and lower substrates of a printed circuit board. Since a height of the stacked BOC packages is greater than a height of a conventional stacked BOC package, the DIMM has a minimum stub length and an optimal topology. Hence, the DIMM can have a signal with excellent fidelity by reducing a load upon a signal line, and installation or wiring of components within the DIMM 300 requires less effort.

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Seongnam-si, South Korea

Byung-Se So