Samsung Electronics Co., Ltd.

Byung-Lyul Park

Gil-heyun Choi

Pil-Kyu Kang

Deok-Young Jung

Dong-chan Lim

Kwang-Jin Moon

Kwang-jin Moon

Suk-chul Bang

Jin-Ho An

Jae-Hwa Park

Ho-jin Lee

Ju-Il Choi

Ji-soon Park

Dae-lok Bae

Tae-Yeong Kim

Kun-sang Park

Jong-myeong Lee

Kyu-ha Lee

Sang-in Lee

Jin-ho Park

Gilheyun Choi

Jin-ho Chun

Seok-Ho Kim

Do-Sun Lee

Jung-Min Ha

Yeun-Sang Park

Joo-Hee Jang

Dae-hong Ko

Hyo-Ju Kim

Sang-Hoon Ahn

Atsushi Fujisaki

Hong-Seong Son

Kyoung-Hee Kim

Seong-min Son

Son-kwan Hwang

Yi-Koan Hong

Hye-Kyung Jung

Zung-Sun Choi

Byung-Hee Kim

Kwangjin Moon

Hyun-Soo Chung

Kyu-Hee Han

Hyeon-Deok Lee

Myoung-Bum Lee

Ji-hwang Kim

Jung-Hwan Oh

Su-Kyoung Kim

Ja-hyung Han

Jum-yong Park

Soyoung Lee

Si-Young Choi

Sang-rok Hah

Tae-Seong Kim

Sanghoon Ahn

Hyunsoo Chung

Jang-Hee Lee

Jinho Park

Jin Ho An

Seung-Woo Shin

Taeseong Kim

Byunghee Kim

Hyoung-sub Kim

Sukchul Bang

Jongmyeong Lee

Ja-Eung Koo

Dong-Kak Lee

Kyoung-hwan Kim

Dosun Lee

Jong-ho Yun

Joong-han Shin

Bong-young Yoo

YongSoon Choi

Hyung-Jun Jeon

SungHee Kang

Tae-woo Kang

Duk-Ho Hong

Sangdon Nam

Jong-min Beak

Ju-Hyuk Chung

Sung-hee Kang

Suk-Chul Bang

Han Kyu-hee

Zungsun Choi

Seung-Mahn Lee

MooJin Jung

Young-gyu Ahn

Hye Kyung Jung

A method of manufacturing a semiconductor device is provided. The method includes forming a preliminary via structure through a portion of a substrate; partially removing the substrate to expose a portion of the preliminary via structure; forming a protection layer structure on the substrate to cover the portion of the preliminary via structure that is exposed; partially etching the protection layer structure to form a protection layer pattern structure and to partially expose the preliminary via structure; wet etching the preliminary via structure to form a via structure; and forming a pad structure on the via structure to have a flat top surface.

Semiconductor devices including through-silicon-vias and methods of manufacturing the same and semiconductor packages including the semiconductor devices

A semiconductor device can include a substrate that has a surface. A via structure can extend through the substrate toward the surface of the substrate, where the via structure includes an upper surface. A pad structure can be on the surface of the substrate, where the pad structure can include a lower surface having at least one protrusion that is configured to protrude toward the upper surface of the via structure.

An integrated circuit (IC) device includes a semiconductor substrate having a via hole extending through at least a part thereof, a conductive structure in the via hole, a conductive barrier layer adjacent the conductive structure; and a via insulating layer interposed between the semiconductor substrate and the conductive barrier layer. The conductive barrier layer may include an outer portion oxidized between the conductive barrier layer and the via insulating layer, and the oxidized outer portion of the conductive barrier layer may substantially surrounds the remaining portion of the conductive barrier layer.

Integrated circuit device including through-silicon via structure and method of manufacturing the same

A method of manufacturing a semiconductor package includes providing a substrate including a mounting region having a recess space for accommodating a semiconductor chip and a connection region surrounding the mounting region, providing a semiconductor chip in the mounting region, the semiconductor chip including a connection pad provided on a top surface of the semiconductor chip, forming a protective layer covering a top surface of the substrate and the top surface of the semiconductor chip, forming a photosensitive insulating layer on the protective layer after forming the protective layer, patterning the photosensitive insulating layer thereby exposing the protective layer, removing the exposed protective layer, and forming a redistribution line to be electrically connected to the connection pad.

Method of manufacturing semiconductor package

A multi-stacked device includes a lower device having a lower substrate, a first insulating layer on the lower substrate, and a through-silicon-via (TSV) pad on the first insulating layer, an intermediate device having an intermediate substrate, a second insulating layer on the intermediate substrate, and a first TSV bump on the second insulating layer, an upper device having an upper substrate, a third insulating layer on the upper substrate, a second TSV bump on the third insulating layer, and a TSV structure passing through the upper substrate, the third insulating layer, the second insulating layer, and the intermediate substrate to be connected to the first TSV bump, the second TSV bump, and the TSV pad. An insulating first TSV spacer between the intermediate substrate and the TSV structure and an insulating second TSV spacer between the upper substrate and the TSV structure are spaced apart along a stacking direction.

Multi-stacked device having TSV structure

A first insulating layer is formed on a substrate. An opening is formed in the first insulating layer. A barrier layer is formed on the first insulating layer and conforming to sidewalls of the first insulating layer in the opening, and a conductive layer is formed on the barrier layer. Chemical mechanical polishing is performed to expose the first insulating layer and leave a barrier layer pattern in the opening and a conductive layer pattern on the barrier layer pattern in the opening, wherein a portion of the conductive layer pattern protrudes above an upper surface of the insulating layer and an upper surface of the barrier layer pattern. A second insulating layer is formed on the first insulating layer, the barrier layer pattern and the conductive layer pattern and planarized to expose the conductive layer pattern. A second substrate may be bonded to the exposed conductive layer pattern.

Method of fabricating multi-substrate semiconductor devices

A semiconductor device includes a via structure and a conductive structure. The via structure has a surface with a planar portion and a protrusion portion. The conductive structure is formed over at least part of the planar portion and not over at least part of the protrusion portion of the via structure. For example, the conductive structure is formed only onto the planar portion and not onto any of the protrusion portion for forming high quality connection between the conductive structure and the via structure.

Semiconductor device and method of fabricating the same

Integrated circuit (IC) devices are provided including a substrate having a first sidewall defining a first through hole that is a portion of a through-silicon via (TSV) space, an interlayer insulating layer having a second sidewall and a protrusion, wherein the second sidewall defines a second through hole providing another portion of the TSV space and communicating with the first through hole, and the protrusion protrudes toward the inside of the TSV space and defines an undercut region in the first through hole, a TSV structure penetrating the substrate and the interlayer insulating layer and extending through the first through hole and the second through hole, and a via insulating layer surrounding the TSV structure in the first through hole and the second through hole.

Integrated circuit devices having through-silicon via structures and methods of manufacturing the same

Wafer processing methods are provided. The methods may include cutting respective edges of a wafer and an adhesive a predetermined angle before grinding a back surface of the wafer.

Wafer processing methods

A semiconductor device includes a via structure penetrating through a substrate, a portion of the via structure being exposed over a surface of the substrate, a protection layer pattern structure provided on the surface of the substrate and including a first protection layer pattern and a second protection layer pattern, the first protection layer pattern surrounding a lower sidewall of the exposed portion of the via structure and exposing an upper sidewall of the exposed portion of the via structure, the second protection layer pattern exposing a portion of the top surface of the first protection layer pattern adjacent to the sidewall of the via structure, and a pad structure provided on the via structure and the protection layer pattern structure and covering the top surface of the first protection layer pattern exposed by the second protection layer pattern.

Semiconductor devices and methods of manufacturing the same

An integrated circuit device is provided which includes a through-silicon via (TSV) structure and one or more decoupling capacitors, along with a method of manufacturing the same. The integrated circuit device may include a semiconductor structure including a semiconductor substrate, a TSV structure passing through the semiconductor substrate, and a decoupling capacitor formed in the semiconductor substrate and connected to the TSV structure. The TSV structure and the one or more decoupling capacitors may be substantially simultaneously formed. A plurality of decoupling capacitors may be disposed within a keep out zone (KOZ) of the TSV structure. The plurality of decoupling capacitors may have the same or different widths and/or depths. An isopotential conductive layer may be formed to reduce or eliminate a potential difference between different parts of the TSV structure.

Integrated circuit device including through-silicon via structure and decoupling capacitor and method of manufacturing the same

A semiconductor device includes a substrate having a die region and a scribe region surrounding the die region, a plurality of via structures penetrating through the substrate in the die region, a portion of the via structure being exposed over a surface of the substrate, and a protection layer pattern structure provided on the surface of the substrate surrounding a sidewall of the exposed portion of the via structure and having a protruding portion covering at least a portion of the scribe region adjacent to the via structure.

Semiconductor devices and methods of manufacturing the same, and semiconductor packages including the semiconductor devices

In a method for fabricating a semiconductor, a first conductive pattern structure partially protruding upwardly from first insulating interlayer is formed in first insulating interlayer. A first bonding insulation layer pattern covering the protruding portion of first conductive pattern structure is formed on first insulating interlayer. A first adhesive pattern containing a polymer is formed on first bonding insulation layer pattern to fill a first recess formed on first bonding insulation layer pattern. A second bonding insulation layer pattern covering the protruding portion of second conductive pattern structure is formed on second insulating interlayer. A second adhesive pattern containing a polymer is formed on second bonding insulation layer pattern to fill a second recess formed on second bonding insulation layer pattern. The first and second adhesive patterns are melted. The first and second substrates are bonded with each other so that the conductive pattern structures contact each other.

Methods of manufacturing a semiconductor device

Semiconductor devices are provided. A semiconductor device includes a substrate, a first conductive structure on the substrate, and a second conductive structure on the first conductive structure. The semiconductor device includes first and second metal-diffusion-blocking layers on respective sidewalls of the first and second conductive structures. The semiconductor device includes an insulating layer between the first and second metal-diffusion-blocking layers. Moreover, the semiconductor device includes a metal-diffusion-shield pattern in the insulating layer and spaced apart from the first conductive structure.

Semiconductor devices

Growing community of inventors

Seoul, South Korea

Byung-Lyul Park