Samsung Electronics Co., Ltd.

Byung-Kwon Cho

Sang-Jine Park

Boun Yoon

Bo-un Yoon

Yong-Sun Ko

Jeong-Nam Han

Sangjine Park

Yong-Jhin Cho

Kee-Sang Kwon

Yeon-Jin Gil

Jiwon Kang

Jongmin Baek

Sanghoon Ahn

Wookyung You

Kun-Tack Lee

Naein Lee

Byunghee Kim

Ji-Hoon Jeong

Jeongnam Han

Hak-Sun Lee

Ha-Young Jeon

Vietha Nguyen

YoungWoo Cho

Songyi Han

Jiwon Yun

Young-ju Park

Inoue Naoya

Wonsang Choi

Young-Hoo Kim

Yongsun Ko

Ji-Hoon Cha

Jihoon Jeong

Jae-Jik Baek

Sukhun Choi

Kwang-Wook Lee

Young Suk Jung

Doo-Sung Yun

Youngtak Kim

Young-sang Youn

Sang-jine Park

Seulgee Jeon

Sangline Park

Wongsang Choi

Jeongman Han

Young-hoo Kim

A substrate processing apparatus includes a vessel providing a processing space for processing a substrate, a substrate support supporting the substrate loaded in the processing space, and a barrier between a side wall of the vessel and the substrate support and surrounding an edge of the substrate supported by the substrate support.

Substrate processing apparatus and apparatus for manufacturing integrated circuit device

A supercritical drying apparatus and a method of drying a substrate, the apparatus including a drying chamber configured to receive a supercritical fluid and to dry a substrate; a chuck in the drying chamber, the chuck being configured to receive the substrate; and a particle remover in the drying chamber, the particle remover being configured to remove dry particles from the substrate by heating the substrate with radiant heat.

Supercritical drying apparatus and method of drying substrate using the same

Disclosed are a supercritical process chamber and an apparatus having the same. The process chamber includes a body frame having a protrusion protruding in an upward vertical direction from a first surface of the body frame and a recess defined by the protrusion and the first surface of the body frame; a cover frame; a buffer chamber arranged between the body frame and the cover frame; and a connector. The buffer chamber includes an inner vessel detachably coupled to the body frame providing a chamber space in the recess and an inner cover detachably coupled to the cover frame. The inner cover is in contact with a first surface of the inner vessel enclosing the chamber space from surroundings. The connector couples the body frame and the cover frame having the buffer chamber arranged therebetween such that the enclosed chamber space is transformed into a process space in which the supercritical process is performed.

Process chamber for a supercritical process and apparatus for treating substrates having the same

A semiconductor device includes a gate spacer defining a trench. The trench includes a first part and a second part sequentially positioned on a substrate. An inner surface of the first part has a slope of an acute angle and an inner surface of the second part has a slope of a right angle or obtuse angle with respect to the substrate. A gate electrode fills at least a portion of the trench.

Methods of forming semiconductor devices including trench walls having multiple slopes

A semiconductor device includes an interlayer insulating layer including a first insulating layer on a substrate, and a plurality of interconnections in the first insulating layer. The interlayer insulating layer includes a first region, and a second region including an air gap. The air gap is defined between a pair of the interconnections in the second region. A top surface of the first insulating layer of the first region is lower than a top surface of at least one of the interconnections in the first region.

Planarized interlayer dielectric with air gap isolation

Semiconductor devices including trench walls having multiple slopes

A semiconductor device is manufactured using dual metal silicide layers. The semiconductor device includes a substrate having first and second regions, a first metal gate electrode on the substrate in the first region, a second metal gate electrode on the substrate in the second region, a first epitaxial layer on and in the substrate at both sides of the first metal gate electrode, a second epitaxial layer on and in the substrate at both sides of the second metal gate electrode, a first metal silicide layer on the first epitaxial layer, a second metal silicide layer on the second epitaxial layer, an interlayer dielectric layer on the first and second metal silicide layers, contact plugs passing through the interlayer dielectric layer and electrically connected to the first and second metal silicide layers.

Semiconductor device having dual metal silicide layers and method of manufacturing the same

A method for forming a trench includes etching an oxide layer to form a trench therein, conformally forming a first reaction layer along a surface of the trench, the first reaction layer including a first region on an upper portion of the trench and a second region on a lower portion of the trench, forming a barrier layer by reacting a first amount of etching gas with the first region of the first reaction layer, and etching the oxide layer on a lower portion of the second region by reacting a second amount of etching gas with the second region of the first reaction layer, the second amount of etching gas being greater than the first amount of etching gas.

Semiconductor device and method of fabricating the same

A method of fabricating semiconductor devices having metal gate electrodes includes forming an insulating layer on a semiconductor substrate having a first region and a second region. The insulating layer is formed to include an interlayer insulating layer and a gate insulation layer. The interlayer insulating layer has first and second grooves respectively disposed in the first and second regions, and the gate insulation layer covers at least bottom surfaces of the first and second grooves. A laminated metal layer is formed on the substrate having the insulating layer. A planarization layer having non-photo sensitivity is formed on the laminated metal layer. The planarization layer in the first region is selectively removed using a dry etching process to expose the laminated metal layer in the first region and to form a planarization layer pattern covering the laminated metal layer in the second region.

Methods of fabricating a semiconductor device including metal gate electrodes

Provided is a method of fabricating a semiconductor device. Gate patterns are formed on a substrate including an NMOS transistor region and a PMOS transistor region. A spacer structure is formed on sidewalls of the gate patterns. The substrate in the PMOS transistor region is etched using the gate patterns and the spacer structure as etching masks, and thereby a recessed region is formed. A compressive stress pattern is formed in the recessed region, and a sidewall of the compressive stress pattern protrudes upwardly from an upper surface of the substrate. A mask oxide layer is formed on a sidewall of the spacer structure. The mask oxide layer is formed to cover a portion of the sidewall of the compressive stress pattern that protrudes upwardly from the upper surface of the substrate.

Semiconductor devices including compressive stress patterns and methods of fabricating the same

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Suwon-si, South Korea

Byung-Kwon Cho