Samsung Electronics Co., Ltd.

Samsung Display Co., Ltd.

Byung-Koan Kim

Ock-chul Shin

Woo-Chul Kim

Ik-Huyn Ahn

Young-chul Rhee

Jong-Hoon Hong

Jong-Sung Lee

Hye-Jin Jung

Woo-chae Jeon

Yeong-cheol Rhee

Se-Moon Oh

Dustin Yuk Lun Wai

A display drive integrated circuit includes a frame buffer, an output selector and a timing controller. The output selector selectively outputs one of image data read from the frame buffer and image data transmitted from a source external to the display drive integrated circuit. The timing controller controls output of the image data read from the frame buffer to the display panel in a self-refresh mode, and controls internal display timing to track external display timing when the display drive integrated circuit exits from the self-refresh mode to control the output selector to output the image data transmitted from the source to the display panel when the internal display timing is synchronized to the external display timing.

Display drive integrated circuit and image display system capable of controlling a self-refresh display

A liquid crystal display includes a display unit displaying an image in response to a driving signal, a driving unit outputting the driving signal to the display unit in response to a plurality of control signal, and a controller outputting the plurality of control signals and image data. The controller includes a plurality of timing controllers providing the image data and the plurality of control signals and a storage device. The plurality of timing controllers share the storage device and may be either connected in series or parallel.

Liquid crystal display

A timing controller provides a cable plug status detection function by receiving a reference lock signal from a graphics system connected via a constituent cable and comparing the reference lock signal to one or more reference time periods to determine the cable plug status.

System and method detecting cable plug status in display device

A domino logic circuit includes an input circuit and an output circuit. The input circuit precharges a dynamic node at a first phase of a clock signal. The input circuit determines a logic level of the dynamic node by performing a logic evaluation of input data at a second phase of the clock signal. The output circuit is coupled between an output node and the dynamic node. The output circuit determines a logic level of the output node in response to the clock signal and the logic level of the dynamic node. The output circuit maintains the logic level of the output node while the logic evaluation is performed.

Domino logic circuit and pipelined domino logic circuit

Growing community of inventors

Suwon-si, South Korea

Byung-Koan Kim