Amkor Technology, Inc.

Anam Semiconductor Inc.

Lucent Technologies Inc.

Byung Joon Han

Young Wook Heo

Thomas Dixon Dudderar

Ju Hoon Yoon

George J Shevchuk

Won Sun Shin

Venkataram Reddy Raju

In Gyu Han

Sung Bum Kwak

King Lien Tai

Sun Ho Ha

Maureen Yee Lau

Robert T Scruton, Sr

Alan E Ferry

The invention relates to a grid array type lead frame having a plurality of leads classified into groups by length. The leads extend to respective lead ends, in each of which at least one different plane direction-converting lead part and/or at least one identical plane direction-converting lead part is formed by at least one bending part, whereby the lead ends are distributed in a grid array. The invention also includes a grid array type lead frame, which is as small as or similar to that of semiconductor chip in area while the lead ends are arrayed on one plane, and are at a farther distance away from neighboring ones but in a higher number per area, in such a manner that they form a grid array.

Grid array type lead frame having lead ends in different planes

A fragile device, such as an integrated circuit chip or a multichip assembly, is packaged by first dispensing a sol surrounding the sides of the device. The sol is laterally confined by means of a rim member typically made of a pre-molded plastic material. The amount of the sol dispensed is not sufficient to run over the top of the rim member. The sol is then heated to form a gel. If desired, a cover member can be put into place onto the top surface of the rim member, for the purpose of additional mechanical protection of the fragile device, for example.

Method of packaging fragile devices with a gel medium confined by a rim

A chip size semiconductor package with a light, thin, simple and compact structure having a reduced size of its semiconductor chip while having an increased number of pins and without degrading its functions. For the package, it is possible to use either the semiconductor chip having bond pads arranged on end portions of the chip or the semiconductor chip having bond pads arranged on the central portion of the chip. In either case, input/output terminals of the package are arranged in the form of an area array. Accordingly, when the package is mounted on an electronic appliance, its mounting area can be minimized, thereby achieving a compactness of the final product.

Semiconductor package and assembly for fabricating the same

A method for reproducing a PCB strip for semiconductor packages, wherein a poor quality PCB unit included in the PCB strip is replaced with a normal quality one, thereby achieving a reduction in the amount of package materials used and an improvement in the process efficiency. The invention also provides a method for fabricating semiconductor packages using the PCB strip reproduction method. A desired portion of a poor quality PCB unit included in a PCB strip is cut out in such a manner that a cutting opening having a peripheral edge extending along the singulation line of the poor quality PCB unit or along a region defined between the singulation line and anti-bending slots of the poor quality PCB unit. In the cutting opening, a separate good quality PCB unit member having the same shape and size as the cutting opening is then fitted. Thus, it is possible to simply and efficiently replace PCB units determined to be of poor quality with separate good quality PCB unit members, respectively.

Method for reproducing printed circuit boards for semiconductor packages

The invention relates to a grid array type lead frame having a plurality of leads classified into groups by length forming a lead end grid array semiconductor package. The leads extend to respective lead ends, in each of which at least one different plane direction-converting lead part and/or at least one identical plane direction-converting lead part is formed by at least one bending part, whereby the lead ends are distributed in a grid array. The invention includes a lead end grid array semiconductor package employing the grid array type lead frame, which is as small as or similar to that of semiconductor chip in area while the lead ends are arrayed on one plane, farther distant way from neighboring ones but in a higher number per area, in such a manner that they form a grid array.

Lead end grid array semiconductor package

A process for manufacturing chip size semiconductor package with a light, thin, and compact structure having a reduced size of its semiconductor chip while having an increased number of pins For the package, it is possible to use either the semiconductor chip having bond pads arranged on end portions of the chip or the semiconductor chip having bond pads arranged on the central portion of the chip. In either case, input/output terminals of the package are arranged in the form of an area array. Accordingly, when the package is mounted on an electronic appliance, its mounting area can be minimized, thereby achieving a compactness of the final product.

Semiconductor package and method for fabricating the same

The present inventors have discovered that fine patterns of metal or insulator can be formed on printed circuit board using conventional lithographic steppers with inverted projection lenses. The inverted projection lenses act as enlargement lenses rather than reducing lenses and exhibit a large depth of focus sufficient to accommodate the deviations of PC board from planarity. The inverted lens reduces the size of the image needed at the mask, permitting multiple mask levels to be combined on a single glass. This reduces the cost of the mask set and permits the use of smaller glass masks having greater accuracy and dimensional stability than the convention mylar masks used for PC board. By inverting the projection lenses on near-obsolete steppers, applicants were able to form metal patterns on PC board of finer dimension than heretofore reported. Inverting a 5.times. ZEISS lens on a GCA 6300A stepper, applicants were able to form vias of less than 25 .mu.m diameter, pattern metal lines and spaces of less than 25 .mu.m, and obtain overlay registration accuracy of less than 25 .mu.m. The field size was larger than 1 in.sup.2, and the depth of focus was greater than 50 .mu.m.

Method and apparatus for forming fine patterns on printed circuit board

The bottom and side surfaces of an electronic device, such as an integrated circuit chip or a multichip assembly, are surrounded by a soft gel medium. The gel medium is laterally confined by a rigid plastic rim that is epoxy-bonded in place along its perimeter. A plate, made of plastic or metal, can be attached to the top surface of the rim, in order to provide a cover for the package.

Growing community of inventors

Seoul, South Korea

Byung Joon Han