Skhynix Inc.

Other

Byung In Lee

Sang Heon Lee

Keon Soo Shim

Hee Joung Park

Jae Il Tak

Hee Youl Lee

Sang Woo Park

Byeong Il Han

Eun Hong Kim

A method for operating a memory device includes providing a memory block including at least one source select transistor coupled between a source line and a bit line, a plurality of memory cells, and a drain select transistor, controlling a source select line coupled to the at least one source select transistor and a plurality of word lines coupled to the plurality of memory cells to be in a floating state, and applying an erase voltage to the source line and the bit line.

Memory device having improved program and erase operations and operating method of the memory device

A semiconductor device includes a memory string connected between a source line and a bit line. The memory string includes first memory cells stacked along a first channel layer, second memory cells stacked along a second channel layer, and at least one switching memory cell connected between the first memory cells and the second memory cells. A method for operating the semiconductor device includes programming a selected first memory cell among the first memory cells, selecting a second memory cell to be programmed among the second memory cells, applying a program voltage to a word line connected to the selected second memory cell, turning off the switching memory cell such that the first channel layer and the second channel layer are electrically isolated from each other, and applying a pass voltage to word lines connected to unselected memory cells among the first and second memory cells.

Semiconductor memory device with a switching memory cell in a memory string and operating method thereof

A memory device includes a memory cell array including a plurality of strings, a peripheral circuit coupled to the memory cell array and configured for sequentially performing a program voltage apply operation, a program verify operation, and a hole injection operation on the plurality of strings, and a control logic configured for controlling an operation of the peripheral circuit, wherein the control logic controls the operation of peripheral circuit to generate Gate Induced Drain Leakage (GIDL) at a channel under a select transistor of each of the plurality of strings during the hole injection operation.

Memory device and operating method of the memory device

A memory device includes a memory cell array having a plurality of memory blocks sharing a source line, a peripheral circuit for performing a program operation and an erase operation on a selected memory block among the plurality of memory blocks, and a control logic for controlling the peripheral circuit. The control logic controls the peripheral circuit such that some source select transistors adjacent to the source line among a plurality of source select transistors included in an unselected memory block among the plurality of memory blocks are floated in a source line precharge operation during the program operation.

A semiconductor memory device is operated by, inter alia, selecting an even bit line or an odd bit line in response to a read command, and precharging the selected bit line by applying a precharge voltage to the selected bit line; changing potential of the selected bit line in response to a threshold voltage of a selected memory cell coupled to the selected bit line; precharging a non-selected bit line by applying a precharge voltage to the non-selected bit line; and sensing read data in accordance with the potential of the selected bit line.

Method of operating a semiconductor memory device

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Growing community of inventors

Hwaseong-si, South Korea

Byung In Lee