Samsung Electronics Co., Ltd.

Byung-Hyun Lim

Sung-Jun Kim

Jong-shin Shin

Hitoshi Okamura

Kwang-Chun Choi

Woo-Chul Jung

Hye-Yeon Yang

A hybrid clock data recovery circuit includes a linear phase detector configured to generate a recovered data signal by sampling an input data signal in response to a clock signal, and to generate up and down signals having a pulse width difference that is linearly proportional to a phase difference between the input data signal and the clock signal. An arbiter is configured to generate a bang-bang up signal representing that a phase of the input data signal leads a phase of the clock signal and a bang-bang down signal representing that the phase of the clock signal leads the phase of the input data signal based on the up and down signals. A digital loop filter is configured to generate a digital control code based on the bang-bang up and down signals. A digitally controlled oscillator is configured to generate an oscillating frequency of the clock signal in response to the digital control code, and to adjust the oscillating frequency of the clock signal in response to the up and down signals.

Hybrid clock data recovery circuit and receiver

A differential driver includes first and second pull-up resistors respectively connected to first and second output terminals, a plurality of differential-input transistor pairs connected each to the first and second output terminals, current sources connected each to the differential-input transistor pairs, and a slew rate controller adapted to generate differential input signals to be applied each to the differential-input transistor pairs in response to an input signal. The slew rate controller may output the differential input signals simultaneously or sequentially.

Differential driver and method capable of controlling slew rate

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Seoul, South Korea

Byung-Hyun Lim