Samsung Electronics Co., Ltd.

Seoul National University

Byung Hyun Lee

Jin Young Yoon

Yoo-Sang Hwang

Sang Do Park

Ki Hwan Kwon

Min Hee Kim

Min-Hee Cho

Chong Am Kim

Eun Bi Seo

Sung-Ok Lee

A semiconductor device, a layout design method for the semiconductor device, and a method for fabricating the semiconductor device are provided. The semiconductor device includes a standard cell region. The semiconductor device includes a substrate including a first surface and a second surface, which are opposite to each other, a first power wiring, which extends in a first direction on the first surface of the substrate, and is configured to provide a first power voltage to the standard cell region, a second power wiring, which extends in the first direction on the first surface of the substrate, is arranged alternately with the first power wiring in a second direction intersecting the first direction, and is configured to provide a second power voltage different from the first power voltage to the standard cell region, a first back routing wiring on the second surface of the substrate, and a plurality of first tab cell regions arranged along the second direction, wherein each of the first tab cell regions includes a first through via, which penetrates the substrate and connects the first power wiring and the first back routing wiring.

Semiconductor device, layout design method for the same and method for fabricating the same

Provided is a multi-pulsed jets generating apparatus including: at least one actuator that generates pulsed jets in a plurality of orifices according to a volume change of a plurality of cavities caused by vibration of at least one diaphragm; and a manifold connected to the at least one actuator so as to generate multi-pulsed jets by receiving the pulsed jets occurring in the plurality of orifices. The velocity and uniformity of the pulsed jets occurring in the plurality of injection ports can be controlled according to vibration phases of a plurality of diaphragms.

Multi-pulse jet generator and air conditioner having same

In a method of fabricating a semiconductor device having an alignment key and a semiconductor device fabricated thereby. The method of fabricating a semiconductor device includes providing a semiconductor substrate having a scribe lane region and a cell region. An etch barrier pattern and a gate pattern are formed on the scribe lane region and the cell region respectively. A first interlayer insulating layer is formed to cover the etch barrier pattern and the gate pattern. A preliminary alignment key pattern and a bit line pattern are formed on the first interlayer insulating layer of the scribe lane region and the cell region respectively. A second interlayer insulating layer is formed to cover the preliminary alignment key pattern and the bit line pattern. The second interlayer insulating layer and the first interlayer insulating layer are patterned to expose the etch barrier pattern, thereby forming an alignment key pattern in the scribe lane region, and concurrently, forming a storage node contact opening in the cell region.

Method of fabricating semiconductor device having alignment key and semiconductor device fabricated thereby

Growing community of inventors

Daegu, South Korea

Byung Hyun Lee