Samsung Electronics Co., Ltd.

Byung-Hyug Roh

Un-Byoung Kang

Tae-Je Cho

Hyeoung-won Seo

Seong-goo Kim

Sang-Min Jeon

Sang-Wook Lee

Min-Jung Kim

Soo-Ho Shin

Sun-Hoo Park

Young-Woong Son

A chip-stacked semiconductor package includes a first chip having a first front surface, a first back surface, and a first connection member on the first front surface, the first back surface being opposite to the first front surface; a second chip having a second front surface, a second back surface, a second connection member and a first through-silicon via (TSV) electrically connected to the second connection member, the second back surface opposite to the second front surface, and the second connection member on the second front face; and a first sealing member between the first front surface and the second front surface, the first sealing member filling a space between the first connection member and the second connection member, the first connection member of the first chip and the second connection member of the second chip being symmetric with respect to each other.

Chip-stacked semiconductor package and method of manufacturing the same

A semiconductor device comprises a semiconductor substrate including a first core region and a second core region between which a cell array region is interposed, a first conductive line and a second conductive line extending to the first core region across the cell array region, and a third conductive line and a fourth conductive line extending to the second core region across the cell array region, wherein a line width of the first through fourth conductive lines is smaller than a resolution limit in a lithography process.

Semiconductor device including conductive lines with fine line width and method of fabricating the same

A semiconductor device includes first gate structures, second gate structures, a first capping layer pattern, a second capping layer pattern, first spacers, second spacers, third spacers, and a substrate having first impurity regions and second impurity regions. The first gate structures are arranged on the substrate at a first pitch. The second gate structures are arranged on the substrate at a second pitch greater than the first pitch. The first capping layer pattern has segments extending along side faces of the first gate structures and segments extending along the substrate. The second capping layer pattern has segments extending along the second gate structures and segments extending along the substrate. The first spacers and the second spacers are stacked on the second capping layer pattern. The third spacers are formed on the first capping layer pattern.

Semiconductor device and method of manufacturing the same

Insulated electrodes are formed by first forming on an integrated circuit substrate, an insulating layer, a conductive layer on the insulating layer, and a metal silicide layer on the conductive layer, and then forming a metal silicon nitride layer on the metal silicide layer. The metal silicon nitride layer acts as a silicon protrusion-preventing layer on the metal silicide layer that prevents formation of silicon protrusions from the metal silicide layer during subsequent processing. Reliability and/or yield problems that are caused by undercutting of an insulation layer in an insulated electrode may also be reduced by forming on an integrated circuit substrate, an insulating layer, conductive layer on the insulating layer and a metal silicide layer on the conductive layer. The metal silicide layer and the conductive layer are selectively etched to define an insulated electrode including a sidewall while also undesirably undercutting the insulating layer relative to the conductive layer thereon to define an undercut region. A conformal silicon nitride layer is coated on the integrated circuit substrate, including on the sidewall and in the undercut region. The conformal silicon nitride layer plugs the undercut insulating layer with silicon nitride, to thereby reduce reliability and/or yield problems.

Integrated circuit insulated electrode forming methods using metal silicon nitride layers, and insulated electrodes so formed

A method for forming a trench isolator in a semiconductor substrate comprises: forming a mask layer on the substrate having a opening defining a trench formation region on the substrate; etching the semiconductor substrate through the opening in the mask to form a trench in the substrate; depositing a trench isolation material on the substrate to fill the trench with the isolation material and form a trench isolator in the substrate; planarization-etching the trench isolation material until a top surface of the mask layer is exposed; and, forming a thin protective layer on the surface of the semiconductor substrate. The thin protective layer prevents an edge dipping effect of the trench isolator during subsequent cleaning processes, and enables the planarization-etching to reduce the thickness of the mask layer to the minimum thickness possible, thereby reducing the stresses applied to the semiconductor substrate by the mask layer during subsequent high temperature annealing processes.

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Yongin-si, South Korea

Byung-Hyug Roh