Samsung Electronics Co., Ltd.

Byung-hun Han

Sung-Jin Park

Jae-Goo Lee

Kyung-Hoon Chung

Byung-kwon An

A voltage stabilizer circuit for alternately or simultaneously stabilizing first and second generated voltages includes shared capacitor connected between the first and second generated voltages. The voltage stabilizer circuit may further include first and second switches for alternately connecting the first and second electrode of the shared capacitor to a ground. The alternation of the stabilized first and second voltages output by the voltage stabilizer circuit can be synchronized with a pixel polarity inversion mode signal output by the internal driver circuit of an LCD display.

Share-capacitor voltage stabilizer circuit and method of time-sharing a capacitor in a voltage stabilizer

A power converting circuit of a display driver includes a positive voltage generator and a negative voltage generator. The positive voltage generator includes a first capacitive DC-DC converter and a first inductive DC-DC converter, and generates a positive source voltage by selectively using one of the first capacitive DC-DC converter, the first inductive DC-DC converter, or a first external power supply voltage. The negative voltage generator includes a second capacitive DC-DC converter and a second inductive DC-DC converter, and generates a negative source voltage by selectively using one of the second capacitive DC-DC converter, the second inductive DC-DC converter, or a second external power supply voltage.

Power converting circuit of a display driver

Provided is a boosting voltage generating element used in a semiconductor integrated circuit, more particularly, is a charge pump. The charge pump includes a first converting unit and a second converting unit. The first converting unit is configured to receive a first voltage in response to a first clock signal to generate a first pumping voltage. The first converting unit is also configured to alternately output the first pumping voltage to a first terminal and a second terminal. The second converting unit is configured to receive the first pumping voltage through the first terminal or the second terminal in response to a second clock signal and a third clock signal respectively, to generate a second pumping voltage The second converting unit is also configured to provide the second pumping voltage to an output terminal. The second converting unit is configured to provide the second pumping voltage to the output terminal for at least half of a period of the second clock signal or the third clock signal.

Charge pump and display driving system including the same

An output buffer capable of reducing the noise and distortion of buffered output data while operating at high speed, and a buffering method performed in the output buffer are provided. An output buffer for buffering input data and outputting buffered input data as output data comprises first through M-th and (M&plus;1)th through (M&plus;N)th delay means for delaying the input data for (M&plus;N) different delay times and outputting one by one delayed data in a predetermined order at time intervals of

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Seoul, South Korea

Byung-hun Han