Samsung Electronics Co., Ltd.

Samsung Mobile Display Co., Ltd.

Samsung Display Devices Co., Ltd.

Samsung Sdi Co., Inc.

Samsung Display Co., Ltd.

Vms Solutions Co.. Ltd.

Byung-Hee Kim

Gil-heyun Choi

Jong-Min Baek

Sang-Hoon Ahn

Eun-Ji Jung

Nae-in Lee

Hee-Sook Park

Jang-Hee Lee

Woong-hee Sohn

Rak-Hwan Kim

Tae-Ho Cha

Jin-Nam Kim

Hyun-Su Kim

Kyu-Hee Han

Jong-Jin Lee

Kyung-In Choi

Jong-Myeong Lee

Eun-Ok Lee

Ju-young Yun

Myoung-Bum Lee

Gil-Heyun Choi

Kyoung-Hee Kim

Jong-myeong Lee

Dae-Yong Kim

Jae-Hwa Park

Byung-Hak Lee

Woo-Kyung You

Eun-ji Jung

Ho-Yun Jeon

Jin-Woo Park

Won-Kyu Kwak

Chang-won Lee

Ho-Kyoon Chung

Kwang-jin Moon

Sun-Hwa Kim

Seong-hwee Cheong

Jeong-gil Lee

Jung-hun Seo

Sang-Woo Lee

Byung-Lyul Park

Sang-in Lee

Jin-ho Park

Hong-bae Park

Min-sang Song

Jong-Ho Yun

Sun-hwa Kim

Sang-Don Nam

Geum-jung Seong

Myoung Seok Lee

Tsukasa Matsuda

Young-il Choi

Jong-ho Yun

Viet Ha Nguyen

Dae-yong Kim

Jae-Won Hwang

Sang-Shin Jang

Jong-min Beak

Seung-Gon Kang

Geum-Jung Seong

Seung-gil Yang

Choong-Ho Lee

Jong-Ho Lee

Sang-min Lee

Tae-Soo Kim

Chang-soo Park

Sang-Bom Kang

Hyun Eok Shin

Sang-Min Lee

In-Sun Park

Won-Jun Lee

Sun Hwa Kim

Woo-Jin Lee

Jae-Won Chang

Dong-Chan Lim

Hyun-Eok Shin

Chan-Kyoung Moon

Kuen-Dong Ha

Yeong-kwan Kim

Mi-Sook Suh

Sug-Woo Jung

Sang-won Lee

Hyun-seok Lim

Seong-Geon Park

Chang-Won Lee

Kyoung-Soo Lee

Dong-won Han

You-Kyoung Lee

Yoon-Chan Oh

In-seon Park

Su-Kyoung Kim

Sang-bum Kang

Young Il Choi

Byung-Iyul Park

Seon-Hee Kim

Kyung-Min Chung

Young-ju Park

Kyoung-Hee Nam

In-Young Jung

Hyun-soo Kim

Han Kyu-hee

Provided is a dispatching method in a factory based on reinforcement learning. The dispatching method in a factory based on reinforcement learning may comprise: constructing a Markov decision process (MDP) for dispatching actions of a dispatcher in the factory and resulting rewards and states of the factory; performing learning by applying reinforcement learning (RL) to the constructed MDP; and as a result of said RL, selecting a job that maximizes a weighted sum of a plurality of scored dispatching rules.

Reinforcement learning and simulation based dispatching method in a factory, and an apparatus thereof

A semiconductor device includes a first insulating interlayer on a first region of a substrate and a second insulating interlayer on a second region of the substrate, a plurality of first wiring structures on the first insulating interlayer, the first wiring structures being spaced apart from each other, a plurality of second wiring structures filling a plurality of trenches on the second insulating interlayer, respectively, an insulation capping structure selectively on a surface of the first insulating interlayer between the first wiring structures and on a sidewall and an upper surface of each of the first wiring structures, the insulation capping structure including an insulating material, a third insulating interlayer on the first and second wiring structures, and an air gap among the first wiring structures under the third insulating interlayer.

Methods of manufacturing semiconductor devices

A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first interlayer insulating layer including a first trench, on a substrate a first liner layer formed along a side wall and a bottom surface of the first trench and including noble metal, the noble metal belonging to one of a fifth period and a sixth period of a periodic chart that follows numbering of International Union of Pure and Applied Chemistry (IUPAC) and belonging to one of eighth to tenth groups of the periodic chart, and a first metal wire filling the first trench on the first liner layer, a top surface of the first metal wire having a convex shape toward a bottom surface of the first trench.

Semiconductor device having a trench with a convexed shaped metal wire formed therein

Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.

Semiconductor devices

A semiconductor device includes an insulating interlayer disposed on a substrate, a first protection pattern, a first barrier pattern, a first adhesion pattern, and a first conductive pattern. The insulating interlayer includes a via hole and a first trench. The via hole extends through a lower portion of the insulating interlayer. The first trench is connected to the via hole and extends through an upper portion of the insulating interlayer. The first protection pattern covers a lower surface and sidewalls of the via hole and a portion of a lower surface and a lower sidewall of the first trench, and includes a conductive material. The first barrier pattern covers the protection pattern and an upper sidewall of the first trench. The first adhesion pattern covers the first barrier pattern. The first conductive pattern is disposed on the first adhesion pattern, and fills the via hale and the first trench.

Semiconductor device with a conductive liner

Semiconductor devices and methods of manufacturing the same

A method of forming a semiconductor device can include forming an insulation layer using a material having a composition selected to provide resistance to subsequent etching process. The composition of the material can be changed to reduce the resistance of the material to the subsequent etching process at a predetermined level in the insulation layer. The subsequent etching process can be performed on the insulation layer to remove an upper portion of the insulation layer above the predetermined level and leave a lower portion of the insulation layer below the predetermined level between adjacent conductive patterns extending through the lower portion of the insulation layer. A low-k dielectric material can be formed on the lower portion of the insulation layer between the adjacent conductive patterns to replace the upper portion of the insulation layer above the predetermined level.

Methods of manufacturing semiconductor devices including conductive structures

A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes an interlayer insulating film, a first trench having a first width, and a second trench having a second width, the second trench including an upper portion and a lower portion, the second width being greater than the first width, a first wire substantially filling the first trench and including a first metal, and a second wire substantially filling the second trench and including a lower wire and an upper wire, the lower wire substantially filling a lower portion of the second trench and including the first metal, and the upper wire substantially filling an upper portion of the second trench and including a second metal different from the first metal.

Semiconductor device and method of fabricating the same

A semiconductor device includes a plurality of wiring structures spaced apart from each other, and an insulating interlayer structure. Each of the wiring structures includes a metal pattern and a barrier pattern covering a sidewall, a bottom surface, and an edge portion of a top surface of the metal pattern and not covering a central portion of the top surface of the metal pattern. The insulating interlayer structure contains the wiring structures therein, and has an air gap between the wiring structures.

In a method of forming a wiring structure, a lower structure is formed on a substrate. An insulating interlayer is formed on the lower structure. The insulating interlayer is partially removed to form at least one via hole and a dummy via hole. An upper portion of the insulating interlayer is partially removed to form a trench connecting the via hole and the dummy via hole. A first metal layer filling the via hole and the dummy via hole is formed. A second metal layer filling the trench is formed on the first metal layer.

Methods of forming wiring structures including a plurality of metal layers

The inventive concept provides porous, low-k dielectric materials and methods of manufacturing and using the same. In some embodiments, porous, low-k dielectric materials are manufactured by forming a porogen-containing dielectric layer on a substrate and then removing at least a portion of said porogen from the layer.

Method of manufacturing a semiconductor device having a porous, low-k dielectric layer

A semiconductor device includes a first main strap, a second main strap, a plurality of first sub straps, a plurality of second sub straps, and a plurality of dummy lines. The first main strap is extended in a first direction. The second main strap is extended in the first direction. A plurality of first sub straps is branched from the first main strap. The plurality of second sub straps is branched from the second main strap. The plurality of dummy lines is positioned between the first main strap and the second main strap. Each of the plurality of dummy lines is positioned between each of the plurality of first sub straps and each of the plurality of second sub straps. Each of the dummy lines is spaced apart from the first main strap, the second main strap, each of the first sub straps and each of the second sub straps.

Semiconductor device with dummy lines

A method of forming through silicon vias (TSVs) uses a low-k dielectric material as a via insulating layer to thereby improve step coverage and minimize resistive capacitive (RC) delay. To this end, the method includes forming a primary via hole in a semiconductor substrate, depositing low-k dielectric material in the primary via hole, forming a secondary via hole by etching the low-k dielectric in the primary via hole, in such a manner that a via insulating layer and an inter metal dielectric layer of the low-k dielectric layer are simultaneously formed. The via insulating layer is formed of the low-k dielectric material on sidewalls and a bottom surface of the substrate which delimit the primary via hole and the inter metal dielectric layer is formed on an upper surface of the substrate. Then a metal layer is formed on the substrate including in the secondary via hole, and the metal layer is selectively removed from an upper surface of the semiconductor substrate.

Method of forming through silicon via of semiconductor device using low-K dielectric material

Growing community of inventors

Seoul, South Korea

Byung-Hee Kim