Seoul National University

Samsung Electronics Co., Ltd.

Snur & Db Foundation

Leland Stanford Junior University

Gachon University of Industry-academic Cooperation Foundation

Kyungpook National University Industry-academic Cooperation Foundation

Hynix Semiconductor Inc.

Incheon University Industry Academic Cooperation Foundation

Byung-Gook Park

Min-Chul Sun

Seongjae Cho

Sungjun Kim

Ki-Whan Song

Jong-Duk Lee

Min-Woo Kwon

Min-Hwi Kim

Tae-Hoon Kim

Sang-Ho Lee

Hyungjin Kim

Jeong-Uk Han

Chung-woo Kim

Il-Han Park

Sung-Taeg Kang

Jae-chul Park

Yong-kyu Lee

Sungmin Hwang

Wandong Kim

Yoon Jae Kim

Yun-Heub Song

Wook-hyun Kwon

Myung-Hyun Baek

Seong Jae Cho

Dae-woong Kwon

In Man Kang

Sunghun Jung

Chang-jung Kim

Jung-Hoon Lee

Hyun Woo Kim

In-gyu Baek

Yong-Kyu Lee

James S Harris, Jr

Kyung-Chang Ryoo

Jang-Hyun Kim

Jeong-Hee Han

Jae Min Jeong

Chan-Jin Park

Kyung-seok Oh

Hoon Jeong

Ji-soo Chang

Soo-Doo Chae

Sang-wan Kim

Jeong-hoon Oh

Sung Hun Jin

Garam Kim

Keun Kee Hong

Sang Yeop Jee

Pil-Jong Kim

Tae-Jin Jang

Seon-Ick Sohn

Won Bo Shim

Song-Ju Lee

Jeong Soo Park

Minhwi Kim

II-Han Park

Tae-Hyeon Kim

Byung Doo Yoo

Jung Han Lee

Chang Su Seo

Taejin Jang

Embodiments relate to a semiconductor device including a body made of a first conducting semiconductor material, a source and a drain made of a second conducting semiconductor material and formed on the body, a first gate formed on the body with a gate insulating layer interposed between the first gate and the body, a second gate formed opposite the first gate with respect to the body, and an insulating layer stack having a charge storage layer formed between the body and the second gate, and a method for controlling a synapse weight of a target semiconductor device within a neural network including semiconductor devices.

Semi-conductor device having double-gate and method for setting synapse weight of target semi-conductor device within neural network

An integrated circuit emulating a neural system and a fabricating method thereof are provided. A synapse device array that imitates a brain neural system (i.e., a central nervous system) requiring high integration on the same substrate is formed by stacking one or more layers on a lower portion, and a neuron circuit of a peripheral nervous system having sensory and motor neurons connected to the brain neural system is formed on an upper portion.

Integrated circuit emulating neural system with neuron circuit and synapse device array and fabrication method thereof

Embodiments relate to an inference method and device using a spiking neural network including parameters determined using an analog-valued neural network (ANN). The spiking neural network used in the inference method and device includes an artificial neuron that may have a negative membrane potential or have a pre-charged membrane potential. Additionally, an inference operation by the inference method and device is performed after a predetermined time from an operating time point of the spiking neural network.

Inference method and device using spiking neural network

A neural network using a cross-point array is provided along with a pattern readout method thereof. Resistive memory devices are stacked vertically to form the neural network as synaptic devices. The connection strength of the signal passing between two neurons is controlled by the positive and negative conductance of the resistive memory devices and it is possible to recognize and readout patterns by learning in the cross-point array.

Neural networks using cross-point array and pattern readout method thereof

A resistive memory device and a method of operation of the resistive memory device are provided. The resistance memory device includes a resistance change layer that has a tunneling film and has many states. The conductance is changed symmetrically in a SET operation and a RESET operation. Thus, the resistive memory device can be used for efficient and accurate data storage as a RRAM in a high-capacity memory array, and as a synaptic device controlling the connection strength of a synapse in a neuromorphic system.

Operation method of resistive memory device

The present invention relates to a resistance change memory, that is, a resistive memory device. By forming a bottom electrode from a doped semiconductor different material from a conventional one, it is possible to fabricate the memory device simultaneously with peripheral circuit elements. By having one or more electric field concentration regions in the bottom electrode, it is possible to reduce the power consumption reducing the voltage. The present invention can be also stacked vertically in any small and apply to the synaptic device array recently attracting the great interest as the next generation computing technology for realizing the neural imitation system.

Resistive random access memory device for 3D stack and memory array using the same and fabrication method thereof

Semiconductor circuits are provided for emulating neuron firing process using a positive feedback transistor having first and second gate electrodes in the longitudinal direction of a channel region. The first gate electrode is connected to a gate electrode of a first p-channel MOSFET to be an input terminal and the second gate electrode is connected to a drain to be applied with a supply voltage. Thus electrons and holes can accumulate separately in a channel region (i.e., a body) under each of the gate electrodes by applying input signals to the input terminal and drastically reduce the wasted power consumption in the non-fired neurons because the current is turned on and off only at a moment that corresponds to a firing of the neuron. Thus, the semiconductor circuits can be driven by low power and have the same level of endurance as a general MOSFET.

Semiconductor circuit using positive feedback field effect transistor for emulating neuron firing process

A resistive random access memory device having a nano-scale tip and a nanowire is provided. A memory array using the same also is provided and fabrication method thereof. A technique is provided for forming a bottom electrode having an upwardly protruding tapered tip structure through etching a semiconductor substrate and a top electrode being formed of a nanowire and a technique forming a resistive random access memory device at a location intersected with each other in order that an area of each memory cell is minimized and that an electric field is focused on the tip of the bottom electrode across the top electrode.

Resistive random access memory device having nano-scale tip and nanowire, memory array using the same and fabrication method thereof

A semiconductor device includes a structure on a substrate and a plurality of gate-all-around devices on the structure. The structure includes a plurality of sacrificial layers and a plurality of active layers alternately stacked on one another. The sacrificial layers have different widths and the active layers have different widths to form multiple stepped layers on the substrate. The gate-all-around devices are on respective ones the multiple stepped layers.

Semiconductor device

The present invention provides a semiconductor circuit for emulating neuron firing process having a floating body device instead of the conventional capacitor. By using a floating body to store excess holes generated by impact ionization, it is possible to emulate signal accumulation of a neuron, trigger firing when the storage is in excess of a predetermined threshold value, and return to an original state after the firing.

Semiconductor circuit using floating body device for emulating neuron firing process

A resistive random access memory device is provided with a tunneling insulator layer between a resistance change layer and a bottom electrode. Thus, it is possible: to raise the selection (on/off) ratio by the current of a direct tunneling induced by low voltage in the unselected cell and the current of an F-N tunneling induced by high voltage in the selected cell, to efficiently suppress the leakage current in the read operation, to make a low current operation less &#x3bc;A level by controlling the thickness of the tunneling insulator layer, and to be simultaneously fabricated together with circuit devices by forming the bottom electrodes (word lines) with a semiconductor material.

Resistive random access memory device embedding tunnel insulating layer and memory array using the same and fabrication method thereof

The present invention relates to a resistive random access memory device having a nano-scale tip, memory array using the same and fabrication method thereof. Especially, the present invention provides a technique forming a bottom electrode having an upwardly protruding tapered tip structure through etching a semiconductor substrate in order that an electric field is focused on the tip of the bottom electrode across a top electrode and that a region where conductive filaments are formed is maximally minimized or localized.

Resistive random access memory device having a nano-scale tip, memory array using the same and fabrication method thereof

A method for fabricating a semiconductor device includes forming a first mask on a substrate, forming a first side wall of a fin by performing a first etching of the substrate using the first mask, forming a second mask on the substrate, the second mask being different from the first mask, and forming a second side wall of the fin by performing a second etching of the substrate using the second mask.

Method for fabricating semiconductor device

A semiconductor device has gate-all-around devices formed in respective regions on a substrate. The gate-all-around devices have nanowires at different levels. The threshold voltage of a gate-all-around device in first region is based on a thickness of an active layer in an adjacent second region. The active layer in the second region may be at substantially a same level as the nanowire in the first region. Thus, the nanowire in the first region may have a thickness based on the thickness of the active layer in the second region, or the thicknesses may be different. When more than one active layer is included, nanowires in different ones of the regions may be disposed at different heights and/or may have different thicknesses.

Semiconductor device with nanowires in different regions at different heights

A semiconductor device comprises a substrate extending in a horizontal direction and a vertical transistor on the substrate. The vertical transistor comprises: a first diffusion region on the substrate; a channel region on the first diffusion region and extending in a vertical direction relative to the horizontal direction of the extension of the substrate; a second diffusion region on the channel region; and a gate electrode at a sidewall of, and insulated from, the channel region. A horizontal transistor is positioned on the substrate, the horizontal transistor comprising: a first diffusion region and a second diffusion region on the substrate and spaced apart from each other; a channel region on the substrate between the first diffusion region and the second diffusion region; and a gate electrode on the channel region and isolated from the channel region. A portion of a gate electrode of the vertical transistor and a portion of the gate electrode of the horizontal transistor are at a same vertical position in the vertical direction relative to the substrate.

Semiconductor devices having vertical device and non-vertical device and methods of forming the same

Growing community of inventors

Seoul, South Korea

Byung-Gook Park