Skhynix Inc.

Byung Goo Cho

Tae Heui Kwon

Sung Hwa Hong

Provided herein may be a memory device for performing a bad block check, a method of operating the memory device, and a method of operating a storage controller communicating with the memory device. The memory device may include a first area including a first memory cell, a second area including a second memory cell, the first memory cell and the second memory cell coupled to an identical word line, and a control circuit configured to perform a first operation on the first area and a second operation on the second area and configured to store a first result indicating whether the first operation has succeeded and a second result indicating whether the second operation has succeeded.

Memory device for performing bad block check, method of operating memory device, and method of operating storage controller communicating with memory device

Provided herein may be a memory device and a method of operating the same. The memory device may include a memory cell array including a plurality of memory blocks, a peripheral circuit configured to perform a read operation of reading data stored in selected memory cells in a target block among the plurality of memory blocks, and a read protection controller configured to control the peripheral circuit to perform a read protection operation of limiting the read operation on memory blocks, among the plurality of memory blocks, corresponding to a read protection command received from a memory controller.

Memory device for performing read protection operation of limiting read operation and method of operating the same

A semiconductor device includes a chip selection signal receiver configured to receive, from an external memory controller, a chip selection signal activating to a state in which communication is possible with the external memory controller. The semiconductor device also includes a data signal receiver configured to receive a command and an address from the external memory controller. The semiconductor device further includes an operation controller configured to perform an internal operation according to the command and the address received through the data signal receiver while the chip selection signal is input. The semiconductor device additionally includes an internal signal generator configured to output an inactivated internal chip selection signal blocking transferal of the chip selection signal to the operation controller when a command other than a command requesting an output of data is received while the internal operation is performed.

Semiconductor device and method of operating the same capable of preventing malfunction during read operation

A semiconductor system includes a controller configured to: select a plurality of fail points based on defect analysis information collected in a process stage, and provide an address designating at least one of the fail points together with a partial reset command; and a semiconductor device including a plurality of functional regions each including one or more of the fail points, the semiconductor device configured to reset, in response to the partial reset command, a sequential circuit disposed in a target functional region corresponding to the address among the functional regions.

Growing community of inventors

Icheon-si, South Korea

Byung Goo Cho