Samsung Electronics Co., Ltd.

Future Wei Technologies, Inc.

Huawei Technologies Co., Limited

Byung Choi

Changho Choi

Yang Seok Ki

Zongwang Li

Krishna Teja Malladi

Guangyu Shi

Rekha Pitchumani

Andrew Zhenwen Chang

Ehsan M Najafabadi

Tong Zhang

Jianming Wu

Da Zhang

Divya Kiran Kadiyala

A system including a scalable memory pool. In some embodiments, the system includes: a first memory node, including a first memory; a second memory node, including a second memory; and a memory node switching fabric connected to the first memory node and the second memory node, the memory node switching fabric being configured to provide access, via the first memory node: with a first latency, to the first memory, and with a second latency, greater than the first latency, to the second memory.

Scalable memory pool

Systems and methods for prefetching data are disclosed. A processor in communication with a storage device identifies a first address. The processor identifies a first setting associated with the first address. The processor issues a first command to a first storage medium of the storage device based on the first setting. The first command is for performing a first type of memory read. The storage device is configured to retrieve first data associated with the first address in the first storage medium, to a second storage medium of the storage device, based on the first command.

Systems and methods for prefetching data

A system includes: a group of memory resources including a first memory node and a second memory node, the first memory node being connected to the second memory node over a switching fabric; and a synchronous clock source connected to the first memory node and the second memory node, the synchronous clock source to provide a synchronized clock signal to the first memory node and the second memory node to synchronize the first memory node with the second memory node. The first memory node and the second memory node are to encode memory data and decode encoded memory data using the synchronized clock signal.

Systems and methods for synchronous cell switching for scalable memory

A multi-dimensional memory cluster. In some embodiments, the memory cluster includes a first node, having an external port for making a connection to a host; a second node, connected to the first node by a first memory-centric connection; the second node storing a service level descriptor; the first node being configured to: receive, from the host, a first request, addressed to the second node, for the service level descriptor; and forward the first request to the second node, the second node being configured to: receive the first request; and send a first response, to the first node, the first response including the service level descriptor of the second node.

Multi-dimensional memory cluster

A system and method for managing memory resources. In some embodiments, the system includes a first memory server, a second memory server, and a server-linking switch connected to the first memory server and to the second memory server. The first server may include a cache-coherent switch and a first memory module. In some embodiments, the first memory module is connected to the cache-coherent switch, and the cache-coherent switch is connected to the server-linking switch.

Disaggregated memory server

A data center network architecture and method for communicating data are provided. The nodes and communication links in the network are arranged according to N dimensions. Groups of four nodes are arranged initially in quad full mesh networks. In each dimension, each node has three connections to other nodes. In particular, in each dimension, the nodes can be arranged in quarters, where a node in one quarter is connected to a node in each of three other quarters. In each dimension, the maximum number of hops between a sending node and a destination node is N. Due to the dimensionality, the nodes and communication links can be easily classified into different service levels, and diagnosis of problems is facilitated.

Quad full mesh and dimension driven network architecture

A method performed by a switch, the method comprising receiving a request for a file from a client, wherein the file is located in a distributed storage system, extracting a directory for the file from the request, performing longest prefix matching (LPM) of the directory against a forwarding information base (FIB) to identify a port, wherein the FIB associates directories with ports of the switch, and forwarding the client request toward a server containing the file via the identified port, wherein the server is one of a plurality of servers in the distributed storage system.

Growing community of inventors

Fremont, CA, United States of America

Byung Choi