Samsung Electronics Co., Ltd.

Byung Chan Ryu

Sang Young Kim

Da Un Jeon

Deok Han Bae

Jong Ho You

Hyung Jong Lee

A semiconductor device includes a substrate, a gate structure on the substrate, a source/drain pattern on the substrate, the source/drain pattern being at a side of the gate structure, a source/drain contact filling on and connected to the source/drain pattern, an entire top surface of the source/drain contact filling being lower than a top surface of the gate structure, and a connection contact directly on and connected to the source/drain contact filling, a top surface of the connection contact being higher than the top surface of the gate structure.

Semiconductor device

A semiconductor device includes a first active region that extends on a substrate in a first direction, a second active region that extends in parallel with the first active region, an element isolation region between the first and second active regions, a gate structure that extends in a second direction different from the first direction, and intersects the first and second active regions, a lower contact spaced apart from the gate structure in the first direction, the lower contact being on the first active region, the element isolation region, and the second active region, and an upper contact on the lower contact between the first active region and the second active region. A width of the lower contact in the first direction that is on the first active region m narrower than a width of the lower contact in the first direction that is on the element isolation region.

A semiconductor device includes a lower interlayer insulating film including a first trench and a second trench adjacent each other; a first gate structure within the first trench and extending in a first direction; a second gate structure within the second trench and extending in the first direction; a source/drain adjacent the first gate structure and the second gate structure; an upper interlayer insulating film on the lower interlayer insulating film; and a contact connected to the source/drain, the contact in the upper interlayer insulating film and the lower interlayer insulating film, wherein the contact includes a first side wall and a second side wall, the first side wall of the contact and the second side wall of the contact are asymmetric with each other, and the contact does not vertically overlap the first gate structure and the second gate structure.

Multi-channel transistor including an asymmetrical source/drain contact

A semiconductor device includes a substrate having a plurality of fins protruding therefrom and an active region on the fins. The device further includes a contact including a conductive region having a concave portion defining an upper portion and a lower portion of the conductive region, an interlayer insulating layer on the active region, and a side insulating layer interposed between the interlayer insulating layer and the lower portion of the conductive region.

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Seongnam-si, South Korea

Byung Chan Ryu