Intel Corporation

Byron R Gillespie

Elliot D Garbus

Ravi S Rao

Bruce A Young

Thomas M Johnson

Dennis M O'Connor

William T Futral

Jay S Heeb

Barry R Davis

Marc A Goldschmidt

Mark A Yarch

Mitchell A Kahn

Joseph Murray

Stephen J Strazdus

Terence Sych

Scott R Tetrick

Richard Brunner

Aravindh Bakthavathsalu

Eliot Garbus

Terry Sych

Dinesh Ranganathan

An I/O subsystem having a processor, a bridge unit, and an I/O messaging unit that couple a primary, secondary and tertiary bus in a computer system. The bridge unit is configurable to claim requests that access a messaging unit (MU) address range from the secondary bus, the MU itself being coupled to the primary bus. The MU interrupts the processor when an I/O request is posted, in response to which the processor reads from the MU pointers to an I/O messages and may then execute the I/O message. To promote the portability of software written for agents on either the primary or the secondary bus that wish to access the MU, the primary and secondary address translation units of the I/O subsystem are programmed to claim the same address translation window, where the MU address range is a portion of the primary ATU address translation window, and the secondary ATU is configured to not claim requests within the MU address range. In a particular embodiment, the I/O subsystem may be implemented as a single integrated circuit chip (I/O processor) which is configured to support the intelligent I/O (IO&#xae;) protocol in connection with Peripheral Components Interconnect (PCI) primary and secondary system busses. By configuring the bridge to claim the MU address range on the secondary bus, the I/O subsystem may permit agents on the secondary bus to perform the IO protocol without interrupting the host processor which normally resides on the primary PCI bus.

Accessing a primary bus messaging unit from a secondary bus through a PCI bridge

Real-time performance monitoring facility in an integrated circuit (IC) data processor for monitoring events related to different bus activity. The monitoring facility is accessible via a bus connection the IC. Events include device acquisition and ownership time, and the number of requests and grants on a given bus. The events are counted as occurrences and durations by a number of event counters integrated in the IC. The IC can notify software when the counters overflow. The IC may feature multiple clock domains, including, for instance, multiple bus interfaces operating at different clock frequencies, in which events from different clock domains may be tracked by the same counter. In one embodiment, the performance monitoring facility is integrated into an I/O processor (IOP) die that complies with the popular intelligent I/O (I O) and Peripheral Components Interconnect (PCI) specifications.

Integrated real-time performance monitoring facility

An application accelerator (AA) unit that in one embodiment is part of an I/O processor (IOP) integrated circuit. The AAU includes logic circuitry for improving the performance of storage applications such as Redundant Array of Inexpensive Disks (RAID). A boolean unit performs operations such as exclusive-or (XOR) on multiple blocks of data to form the image parity block which is written to the redundant disk array. The AAU is associated with a memory-mapped programming interface that allows software executed by a core processor in the IOP to utilize the AAU for accelerating RAID storage applications as well as local memory DMA-type transfers, using the descriptor construct.

Boolean and movement accelerator

An application accelerator unit (AAU) that is integrated as part of a data processor, such as an I/O processor (IOP) integrated circuit. In one embodiment, the AAU includes logic for improving the performance of storage applications such as Redundant Array of Inexpensive Disks (RAID). The AAU performs boolean operations such as exclusive-or (XOR) on multiple blocks of data to form the image parity block which is then written to the redundant disk array. Additionally, the AAU may feature adder logic configured to perform an addition such as a network header checksum calculation on each data packet. The AAU includes a memory-mapped programming interface that allows software executed by a core processor in the IOP to utilize the AAU for accelerating storage and networking applications as well as for local memory DMA-type transfers, using the chain descriptor construct.

Data processor having integrated boolean and adder logic for

An alignment logic circuit transferring segments of data from a first storage device to a second storage device is provided. The alignment logic circuit includes a first and second alignment stages, and an alignment control logic that controls the first and second alignment stages such that the first alignment stage outputs data aligned in a first dimension according to a second configuration, and the second alignment stage outputs data aligned in a second dimension according to the second configuration. A computer system with a DMA controller with a Memory Write and Invalidate logic circuit is provided. The Memory Write and Invalidate logic circuit generates a Memory Write and Invalidate enable signal when the DMA byte count is greater than or equal to a cacheline size, and the current transfer adders is a multiple of the cacheline size. A computer system including a host processor, a first bus coupled to the host processor, a second bus, slave circuit coupled to the second bus, and a direct memory access (DMA) controller is also provided. The DMA controller includes a DMA error handling logic, coupled to the host processor, for receiving a retry signal indicative of a retry request of the slave circuit. The DMA error handling logic also receives an error signal indicative of an error on the first bus and a DMA IDLE. The error handling logic aborts a DMA transfer when the error signal and the DMA signal are asserted and the retry signal is deasserted.

Direct memory access controller

An element of a multi-functional device that integrates a high performance processor into a PCI to PCI bus bridge (P2P). The invention is part of a design that consolidates a high performance processor (the local processor) and other processing elements into a single system which utilizes a local memory. Four PCI interrupt inputs are provided which can be routed to either local processor interrupt inputs or to PCI Interrupt output pins. In this manner, a server designer is able to connect the PCI interrupts directly to the local processor without any jumpers to provide configuration. Additionally, by providing software which would execute on the local processor, the local processor system can intercept the PCI interrupts and process the low level interrupts to create an intelligent I/O subsystem. A simple multiplexor is used to direct the PCI interrupts inputs to the local processor or directs the PCI interrupt inputs directly to the PCI interrupt outputs. The PCI interrupt inputs would be interrupts from PCI devices connected to the secondary PCI bus or PCI add-in cards connected to the secondary PCI bus. The PCI outputs would go directly to an interrupt controller which supports the host processor interrupt structure. This PCI interrupt output mechanism supports the ability to have the local processor intercept the PCI interrupts, determine if the local processor should process the interrupt or forward the interrupt upstream to the host.

Programmable PCI interrupt routing mechanism

A method and apparatus for providing overlay memory support for ball grid array (BGA) microprocessor packages. A emulator having an overlay memory and an emulator probe is provided. The emulator is connected via the emulator probe to a target printed circuit board (e.g., adapter card). This target board includes a local processor, a local memory, a memory controller, and a local processor bus that couples them together. The local processor, local processor bus, and memory controller are integrated into a BGA chip package. Typically, the local processor executes software programs stored in the local memory. Upon receipt of a first signal, the memory controller disables the local memory and allows the emulator to drive data from the overlay memory onto the local processor bus so that the local processor may execute software programs included in the overlay memory.

Method and apparatus for providing emulator overlay memory support for

An integrated circuit for providing multiple configuration modes in a multi-funtion intelligent bridge that includes an integrated processor. A first circuit, coupled to a first external bus, for selectively generating retry cycles onto the first external bus in response to a retry signal is provided. A second circuit, coupled to a local processor, for selectively resetting a local processor that is integrated in the intelligent bridge in response to a reset signal is provided. The first and second circuit, in conjunction with the retry signal and the reset signal, selectively provides one of a multiple number of configuration reset modes for the multi-function intelligent bridge.

Method and apparatus for providing multiple configuration reset modes

A method and system for booting a first processor from a remote memory. In response to a reset signal, a processor which has no associated local memory is prevented from executing code and particularly its boot sequence. Because the first processor is prevented from initializing its environment, configuration cycles from a host processor should be prevented from configuring that environment until the first processor has booted. By preventing the host processor from configuring, the first processor environment's integrity is protected. Because the first processor has no local memory, address cycles generated to access local memory would normally go unclaimed on a local bus. An interface between the local bus and the remote memory is configured to claim the local memory address range from the local bus. Once the first processor is enabled, the local memory addresses are used to access the remote memory to return the necessary boot code.

System for booting processor from remote memory by preventing host

A computer system is provided including a local memory, a local bus coupled to the local memory, a peripheral bus and a direct memory access (DMA) controller. The DMA controller performs DMA transfers of data between the local bus and the peripheral bus. The DMA includes a DMA queue for storing data to be transferred and a bus ownership status circuit for determining bus ownership status of the DMA controller. The DMA controller further includes a local bus interface circuit coupled to the DMA queue and to the status circuit for halting the transfer of data from the local bus to the DMA queue without relinquishing DMA ownership over the local bus when the DMA queue is full and the status circuit indicates that the DMA controller has ownership over both the peripheral bus and the local bus.

Direct memory access controller with interface configured to generate

A method and apparatus for interfacing a device which is compliant to a first bus protocol to a second bus having a second protocol and for providing virtual functions through an intelligent bridge. The interface apparatus is coupled to the first bus and the second bus. The interface device detects a configuration cycle on the second bus and translates the configuration cycle into a corresponding cycle in a format understandable by the first bus. The bus cycle is executed on the first bus. A local processor is interrupted by the interface apparatus. A verification and correction program is executed by the local processor to restore configuration header values if the executed bus cycle violated the protocol of the second bus. The interface apparatus insures that requests for access to the first bus are blocked during the execution of the verification and correction program.

Method and apparatus for interfacing a device compliant to a first bus

Dynamic appending of chain descriptors is described with reference to a computer system having a host processor, a DMA unit, a host memory and an external memory wherein the DMA unit controls transference of data between the host memory and the external memory based upon data transference parameters specified in chain descriptors created by the host processor and stored as data structures within the host memory. In accordance with one method and apparatus described herein, dynamic appending of chain descriptors is achieved by employing a resume bit stored within a register of the DMA unit. The host processor, upon creating a new group of chain descriptors to be appended to a previous group, updates a link value within a last chain descriptor of the previous group to point to the first chain descriptor of the new group and also sets the resume bit within the DMA unit. The DMA unit reads chain descriptor parameters, including link values, they perform a data transfer operation specified by the chain descriptor parameters. Upon completion of the transfer operation, the DMA unit examines the resume bit and, if set, the DMA unit rereads the link value for the current chain descriptor. If the resume bit has not been reset, the DMA unit merely proceeds to process the next chain descriptor specified by the previously read link value or, if that link value is a null value, the DMA unit merely terminates operation. In an alternative embodiment described herein, the host processor updates link values but does not set a resume bit within the DMA unit. Rather, the DMA unit initially reads all parameters for a chain descriptor except for the link value. Then, after completion of the data transfer operation specified by the chain descriptor, the data unit reaccesses the chain descriptor to read the link value. Hence, if the link value is updated by the host processor while the DMA unit is processing a chain descriptor, the DMA unit will nevertheless access the updated link value upon completion of the data transference operation. Method and apparatus embodiments are described herein.

System for creating new group of chain descriptors by updating link

The system and method described provide for the detection and protection of memory accesses without the overhead typically incurred by memory management units. The processor includes a guarded memory unit, which monitors memory accesses to be performed by monitoring transmissions across the memory bus. The guarded memory unit includes a plurality of registers which identify memory addresses and modes which can cause a memory protection or detection violation to occur. If a memory protection violation occurs, a cancel signal is issued to cancel the memory operation prior to completion in order to protect the memory from unauthorized accesses. If a memory violation is detected, the memory operation is permitted to complete and a fault signal is issued to the processor to identify that a memory violation has been detected. As the structure of the protection mechanism does not require separate cycles in the processor, and simply monitors the memory bus for memory accesses, memory protection and detection can be performed with no additional overhead at the processor.

System for protecting memory accesses by comparing the upper and lower

A microprocessor system utilizing an in-circuit emulator (ICE) to aid in testing and debugging by an external emulator. The microprocessor operates in two modes. One mode is emulation mode in which the microprocessor outputs trace information for allowing the emulator to reconstruct microprocessor execution, and the other mode is interrogation mode where the microprocessor ceases emulation mode, and allows the emulator to modify the state of the microprocessor or interrogate it. An ICEBRK signal is provided on the microprocessor to better handle transition from emulation to interrogation mode. An address mark counter and generator is provided to force the microprocessor to automatically issue an address mark message which includes the location of the microprocessor's instruction pointer. An AMCTRL bit may be further provided to allow a human user to selectively inhibit the issuance of an address mark. An ICELOCK signal is provided on the microprocessor to control the writing of control registers during hardware and software initialization that the microprocessor performs. A MSGFRM signal is provided to aid the emulator in capturing trace information generated at high frequencies (in excess of 40 MHz).

Growing community of inventors

Phoenix, AZ, United States of America

Byron R Gillespie