Texas Instruments Corporation

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Byron Lovell Williams

Thomas Dyer Bonifield

Jeffrey Alan West

Honglin Guo

Elizabeth Costner Stewart

David Leonard Larkin

Shrinivasan Jaganathan

Anant Shankar Kamath

John Kenneth Arch

Raja Selvaraj

Licheng Marshal Han

Satyavolu Srinivas Papa Rao

Jose L Melendez

Kenneth D Brennan

Asad Mahmood Haider

Weidong Tian

Darius Lammont Crenshaw

Maxwell Walthour Lippitt, Iii

Dhaval Atul Saraiya

Salvatore Frank Pavone

Hung-Yu Chou

John Britton Robbins

Scott Kelly Montgomery

Maxim James Franke

C Matthew Thompson

Yu-Pei Chen

Jason Chien

Mrinal Kanti Das

Betty S Mercer

Arvin Nono Verdeflor

Sheng-Wen Huang

Michael Andrew Serafin

Sandra Rodriguez Varela

Chien-Chang Li

Anderson Li

Zi-Xian Zhan

Scott Robert Summerfelt

Binghua Hu

Ricky A Jackson

Tsen-Hwang Lin

Alwin J Tsao

Hisashi Shichijo

Alec James Morton

Stephen Arlon Meisner

Bo-Hsun Pan

Steven Alan Lytle

Jeff A West

Erika Leigh Shoemaker

Jay Sung Chun

Lee Alan Stringer

Laurinda W Ng

James Wayne Klawinsky

Stephen Fredrick Clark

Fred Percy Debnam, Ii

Thomas Dyer Bonifeld

Matthew Shawn Fortner

Dewayne Irwin

Wallace W Martin

Tim A Taylor

Shawn Martin O'Connor

Darryl Lewis

An electronic device includes a first dielectric layer above a semiconductor layer, lower-bandgap dielectric layer above the first dielectric layer, the lower-bandgap dielectric layer having a bandgap energy less than a bandgap energy of the first dielectric layer, a first capacitor plate above the lower-bandgap dielectric layer in a first plane of first and second directions, a second dielectric layer above the first capacitor plate, a second capacitor plate above the second dielectric layer in a second plane of the first and second directions, the first and second capacitor plates spaced apart from one another along a third direction, and a conductive third capacitor plate above the second dielectric layer in the second plane, the third capacitor plate spaced apart from the second capacitor plate in the second plane.

Standalone isolation capacitor

A galvanic isolation capacitor device includes a semiconductor substrate and a PMD layer over the semiconductor substrate. The PMD layer has a first thickness. A lower metal plate is over the PMD layer and an ILD layer is on the lower metal plate; the ILD layer has a second thickness. A ratio of the first thickness to the second thickness is between about 1 and 1.55 inclusive. A first upper metal plate over the ILD layer has a first area and a second upper metal plate over the ILD layer has a second area; a ratio of the first area to the second area is greater than about 5. The galvanic isolation capacitor device can be part of a multi-chip module.

Standalone high voltage galvanic isolation capacitors

An electronic device includes a bond wire with a first end bonded by a ball bond to a planar side of a first conductive plate, and a second end bonded by a stitch bond to a conductive stud bump at an angle greater than or equal to 60 degrees. A wirebonding method includes bonding the first end of the conductive bond wire to the first conductive plate includes forming a ball bond to join the first end of the conductive bond wire to a planar side of the first conductive plate by a ball bond, and bonding the second end of the conductive bond wire to the conductive stud bump includes forming a stitch bond to join the second end of the conductive bond wire to the conductive stud bump.

Stud bump for wirebonding high voltage isolation barrier connection

An IC includes a substrate including circuitry configured to provide a receiver or a transmitter circuit. A metal stack is over the semiconductor surface including a top metal layer and a plurality of lower metal layers. An isolation capacitor includes the top metal layer as a top plate that is electrically connected to a first node; and a top dielectric layer on the top plate with a top plate dielectric aperture. One of the plurality of lower metal layers provides a bottom plate that includes a plurality of spaced apart segments. A capacitor dielectric layer is between the top and bottom plate. The segments include a first segment electrically connected to a second node and at least a second segment electrically connected to a third node, with separation regions located between adjacent spaced apart segments. The top plate covers at least a portion of each of the separation regions.

IC including capacitor having segmented bottom plate

Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include an isolator structure with parallel conductive elements forming a capacitor or inductive transformer, overlying a semiconductor structure including a well region of a first conductivity type formed within an tank region of a second conductivity type. The tank region is surrounded by doped regions and a buried doped layer of the first conductivity type, forming a plurality of diodes in series to the substrate. The junction capacitances of the series diodes have the effect of reducing the parasitic capacitance apparent at the isolator.

Device isolator with reduced parasitic capacitance

In a described example, an apparatus includes: a package substrate having a die mount portion and lead portions spaced from the die mount portion; a semiconductor die over the die mount portion having bond pads on an active surface facing away from the package substrate; non-gold bond wires forming electrical connections between at least one of the bond pads and one of the lead portions of the package substrate; a bond stitch on bump connection formed between one of the non-gold bond wires and a bond pad of the semiconductor die, comprising a stitch bond formed on a flex stud bump; and dielectric material covering a portion of the package substrate, the semiconductor die, the non-gold bond wires, the stitch bond and the flex stud bump, forming a packaged semiconductor device.

Semiconductor device packages with high angle wire bonding and non-gold bond wires

Described examples include a hybrid circuit having a component. The component has a first conductive element on a substrate having a configuration and having a first periphery and having an extension at the first periphery. The component also has a dielectric on the first conductive element. The component also has a second conductive element having the configuration on the dielectric that is proximate to and aligned with the first conductive element, and has a second periphery, the extension of the first conductive element extending past the second periphery.

Passive components with improved characteristics

A packaged multichip device includes a first IC die with an isolation capacitor utilizing a top metal layer as its top plate and a lower metal layer as its bottom plate. A second IC die has a second isolation capacitor utilizing its top metal layer as its top plate and a lower metal layer as its bottom plate. A first bondwire end is coupled to one top plate and a second bondwire end is coupled to the other top plate. The second bondwire end includes a stitch bond including a wire approach angle not normal to the top plate it is bonded to and is placed so that the stitch bond's center is positioned at least 5% further from an edge of this top plate on a bondwire crossover side compared to a distance of the stitch bond's center from the side opposite the bondwire crossover side.

Wire bonding between isolation capacitors for multichip modules

An integrated circuit and methods for packaging the integrated circuit. In one example, a method for packaging an integrated circuit includes connecting input/output pads of a first integrated circuit die to terminals of a lead frame via palladium coated copper wires. An oxygen plasma is applied to the first integrated circuit die and the palladium coated copper wires. The first integrated circuit die and the palladium coated copper wires are encapsulated in a mold compound after application of the oxygen plasma.

Integrated circuit packaging

Methods of fabricating a thick oxide feature on a semiconductor wafer include forming a oxide layer having a thickness of at least six micrometers and depositing a photoresist layer on the oxide layer. The oxide layer has a first etch rate of X with a given etchant, the photoresist layer has a second etch rate of Y with the given etchant and the ratio of X:Y is less than 4:1. Prior to etching the photoresist layer and the oxide layer, the photoresist layer is patterned with a grayscale mask that creates a photoresist layer having a sidewall that forms an angle with the horizontal that is less than or equal to 10 degrees.

Method of fabricating a thick oxide feature on a semiconductor wafer

A semiconductor die includes a plurality of layers, the plurality of layers having a top surface. A scribe seal is located in the plurality of layers and includes a first metal stack having a first metal layer located proximate the top surface. A trench is located in at least one layer of the plurality of layers. The trench extends from the top surface of the plurality of layers and is located a distance from the first metal stack. An electrical insulating layer is located on the top surface. The electrical insulating layer covers at least a portion of the top surface adjacent the first metal layer and extends a distance from the top surface of the first metal layer.

Scribe seals and methods of making

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Plano, TX, United States of America

Byron Lovell Williams