Texas Instruments Corporation

Byron Joseph Palla

Brian Keith Kirkpatrick

Douglas Ticknor Grider

Abbas Ali

Stephen A Keller

Brian Edward Hornung

Christopher Scott Whitesell

Stephanie Leanne Hilbun

Forming an integrated circuit, for example by first, concurrently forming a first front end of line (FEOL) layer having a first thickness and a surface contacting or facing a semiconductor substrate frontside and a second FEOL layer, having a second thickness and including a same material as the first FEOL layer and having a surface contacting or facing a semiconductor substrate backside, and second, processing the second FEOL layer to reduce the second thickness.

Reduced semiconductor wafer bow and warpage

A method of forming an integrated circuit includes forming a first layer having a first material type over a first side of a semiconductor wafer. A second layer having a second different material type is removed from a second opposing side of the semiconductor wafer using a first process that removes the second material type at a greater rate than the first material type. Subsequent to removing the second layer, the first layer is removed using a second different process.

Method for stripping one or more layers from a semiconductor wafer

An integrated circuit is formed by identifying process parameters of a plurality of process steps for the first partial lot containing the integrated circuit; confirming the number of wafers in the first partial lot is less than the wafer carrier capacity; examining lots upstream of the partial lot and identifying a second partial lot which can be combined with the first partial lot into a single wafer carrier and which can be processed with the first partial lot; combining the wafers of the partial lots into a single wafer carrier; processing the partial lots through the plurality of process steps; and performing a multi-lot verification process. The multi-lot verification process determines if all wafers in the partial lots have completed the process step; determines if any wafers in the partial lots are on hold; and determining if all wafers in the partial lots are in a same material carrier.

Semiconductor manufacturing optimization by combining small lots into individual carriers

Disclosed are a semiconductor wafer () having a front side laser scribe () and the methods for manufacturing the same. The methods of the invention include the formation of a scribe foundation () on the front side of the semiconductor wafer () designed to accept laser scribing (), and laser scribing the scribe foundation (). Disclosed embodiments include a semiconductor wafer () having a scribe foundation () of layered dielectric () and metal () on the front side. According to disclosed embodiments of the invention, the formation of a scribe foundation () is performed in combination with the formation of a top level metal layer () on the semiconductor wafer () methods for manufacturing.

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Murphy, TX, United States of America

Byron Joseph Palla