Micron Technology Incorporated

Byron D Harris

Daniel A Boals

Karl David Schuh

Abedon Madril

Scheheresade Virani

Amy Lee Wohlschlegel

Sanjay Subbarao

Johnny A Lam

Tom V Geukens

Vivek Shivhare

Samyukta Mudugal

Nathaniel Wessel

John J Kane

Andrei Konan

Oyvind Haehre

Systems and methods are disclosed including for enabling a memory sub-system to perform firmware-based monitoring of system state information without adding latency to the memory sub-system. In an example, a first central processing unit (CPU) of a memory subsystem controller sends, to a second CPU of a memory subsystem controller, an address range. In response to a timer expiring and the second CPU being in an idle state, the second CPU retrieves a log file stored at the address range and sends the log file to a host system.

Internal resource monitoring in memory devices

A total count for an address mapping table is maintained, wherein the total count reflects a total number of updates to the address mapping table, and wherein the address mapping table comprises a plurality of sections. Respective section counts for the plurality of sections are maintained, wherein each respective section count reflects a total number of updates to a corresponding section. It is determined that the total count for the address mapping table satisfies a threshold criterion. A first section of the plurality of sections with a highest section count is identified based on the respective section counts. The first section of the address mapping table is written to a non-volatile memory device.

Managing power loss recovery using a dirty section write policy for an address mapping table in a memory sub-system

Apparatuses and methods for read source determination are provided. One example apparatus can include a controller configured to determine a source for read requests and to direct read requests for a first portion of data to a first block of single level memory cells in response to an amount of a second portion of data written to a second block of single level memory cells being less than a threshold amount, and direct read requests for the first portion of data to a first block of quad level memory cells in response to the amount of the second portion of data written to the second block of single level memory cells being at least the threshold amount.

Read source determination

Systems and methods are disclosed for enabling a memory sub-system to perform firmware-based monitoring of system state information without adding latency to the memory sub-system. The memory sub-system controller can include multiple CPUs which can be employed to perform different tasks. The memory sub-system controller can employ one of the frontend CPUs as a monitoring CPU capable of executing a data-gathering task to retrieve system state information from another CPU.

A journal count reflecting a number of logical-to-physical (L2P) journals written to a non-volatile memory device is maintained, wherein each L2P journal is associated with one or more updates to an L2P address mapping table. In response to determining that the journal count satisfies a threshold criterion, a first section of a plurality of sections of the L2P address mapping table is identified, wherein the plurality of sections of the L2P address mapping table is cached in a volatile memory device. The first section of the L2P address mapping table is written to the non-volatile memory device.

Managing power loss recovery using an oldest section write policy for an address mapping table in a memory sub-system

Various embodiments provide for deferring adjustment of a zone in a memory system or sub-system that supports zones. In particular, some embodiments provide for deferred adjustment of a zone based on detection of an error in a block of an unassigned block set, which can be tracked using a counter.

Deferred zone adjustment in zone memory system

Methods, systems, and devices for plane balancing in a memory system are described. A memory system may select a memory die for writing a set of data. The memory die may include a plurality of planes each of which may include a respective plurality of blocks of memory cells. Based on selecting the memory die, the memory system may determine a first plane of the plurality of planes that has a first quantity of blocks with an availability status and a second plane of the plurality of planes that has a second quantity of blocks with the availability status. The memory system may write the set of data to the plurality of planes, excluding at least the first plane, based at least in part on the first quantity of blocks and the second quantity of blocks.

Plane balancing in a memory system

A logical-to-physical (L2P) table is maintained, wherein a plurality of sections of the L2P table is cached in a volatile memory device. A total dirty count for the L2P table is maintained, wherein the total dirty count reflects a total number of updates to the L2P table. Respective section dirty counts for the plurality of sections are maintained, wherein each respective section dirty count reflects a total number of updates to a corresponding section. It is determined that the total dirty count for the L2P table satisfies a threshold criterion. In response to determining that the total dirty count for the L2P table satisfies the threshold criterion, a first section of the plurality of sections is identified based on the respective section dirty counts. The first section of the L2P table is written to a non-volatile memory device.

A data item is programmed to a first set of management units (MUs) associated with a first portion of one or more memory devices. The first portion includes memory cells of a first type. The first set of MUs is associated with a first physical address. A mapping is generated in a virtual MU data structure that associates the first physical address with a set of virtual MUs associated with the one or more memory devices. An entry associated with the data item is added to a logical-to-physical (L2P) table associated with the one or more memory devices. The entry includes an identifier associated with the set of virtual MUs associated with the one or more memory devices. A detection is made that the data item is programmed to a second set of MUs associated with a second portion of the one or more memory devices. The second portion includes memory cells of a second type. The second set of MUs is associated with a second physical address. The mapping is updated to associate the set of virtual MUs with the second physical address.

Virtual management unit scheme for two-pass programming in a memory sub-system

A zone is loaded onto a first memory component of a storage system, wherein the zone comprises one or more regions of data blocks comprising a first plurality of logical block addresses (LBAs), and a snapshot of each of the one or more regions is stored on a second memory component of the storage system and is associated with a version identifier. A particular version identifier associated with a respective snapshot of a region is identified, and a set of journals stored on the second memory component are identified, wherein the set of journals comprise a second plurality of LBAs mapped to a second plurality of physical block addresses. The one or more regions of the zone are reconstructed, wherein the reconstructing comprises reading the second plurality of LBAs of the set of journals to identify a first logical block address (LBA) that matches with a second LBA within the first plurality of LBAs on the loaded zone on the first memory component, and updating a physical block address corresponding to the second LBA on the loaded zone with a physical block address corresponding to the first LBA from the set of journals.

Zone based reconstruction of logical to physical address translation map

A logical-to-physical (L2P) address mapping table is maintained, wherein a plurality of sections of the L2P address mapping table is cached in a volatile memory device. A journal entry count is maintained reflecting a number of L2P journal entries associated with an L2P journal. It is determined that the journal entry count satisfies a first threshold criterion. In response to determining that the journal entry count satisfies the first threshold criterion, a writing of the L2P journal to a non-volatile memory device is triggered. A written journal count reflecting a number of L2P journals written to the non-volatile memory device is maintained. In response to determining that the written journal count satisfies a second threshold criterion, a first section of the plurality of sections of the L2P address mapping table is identified. The first section of the L2P address mapping table is written to the non-volatile memory device.

A write command is received, for example, from a host system, which operates on a first logical address range. A read command is received that specifies a second logical address range that matches the first logical address range. Responsive to determining that a deallocate command has been received after the write command, zero-filled data is returned in response to the read command.

Efficient processing of commands in a memory sub-system

A plurality of generators that each correspond to a respective one of a plurality of cursors associated with the plurality of memory devices are identified. A sequence of logical unit numbers (LUNs) of a plurality of sequences of LUNs are generated for each of the cursors based on a respective generator corresponding to the plurality of cursors. Each of the cursors are directed to perform a memory operation on a set of LUNs in an order provided by the sequence of LUNs that is associated with each of the plurality of cursors.

Per cursor logical unit number sequencing

Systems and methods for storing and validating namespace metadata are disclosed. An exemplary system includes a memory component and a processing device receiving a first read instruction from a host process. The first read instruction includes a namespace offset. A first logical address is generated by combining a namespace identifier for the namespace assigned to the host process and the namespace offset. The first logical address is translated into a first physical address using a plurality of hierarchical tables. A second read instruction, which includes the first physical address and the first logical address, is generated. The second read instruction is sent to a memory component. The memory component validates the translation of the first logical address by comparing the first logical address in the second read instruction to metadata associated with data to be read at the first physical address.

Error-checking in namespaces on storage devices

A read command is received from a host system, which operates on a first logical block address (LBA) range that at least partially overlaps with a second LBA range associated with a write command. A state associated with the write command is determined, where the state is indicative of whether a logical-to-physical (L2P) mapping table has been updated based on the write command. Data corresponding to the first LBA range is transmitted to the host system based on the state associated with the write command.

Growing community of inventors

Mead, CO, United States of America

Byron D Harris